San Diego, CA · On-site
$144K - $176K/yr
Design Verification Engineer Job Type : Full time Location : San Diego And Bay Area : Strong verification skills: test planning, problem solving, debug, adversarial testing. Multimedia Camera Image ...
San Diego, CA · On-site
$144K - $176K/yr
Design Verification Engineer Job Type : Full time Location : San Diego And Bay Area : Strong verification skills: test planning, problem solving, debug, adversarial testing. Multimedia Camera Image ...
Austin, TX · On-site
$134K - $164K/yr
Senior Design Verification Engineer ID: 1064 Location: Austin, TX More about this job > Description Senior Design Verification Engineer Looking for new challenges? Would you like the variety of a ...
Austin, TX · On-site
$134K - $164K/yr
Senior Design Verification Engineer ID: 1064 Location: Austin, TX More about this job > Description Senior Design Verification Engineer Looking for new challenges? Would you like the variety of a ...
Palo Alto, CA · On-site
$120K - $225K/yr
We're hiring experienced Design Verification Engineers from junior to senior levels to play a key role in developing and verifying the designs that will bring our next-generation AI processors to ...
Palo Alto, CA · On-site
$120K - $225K/yr
We're hiring experienced Design Verification Engineers from junior to senior levels to play a key role in developing and verifying the designs that will bring our next-generation AI processors to ...
$120K - $225K/yr
We're hiring experienced Design Verification Engineers from junior to senior levels to play a key role in developing and verifying the designs that will bring our next-generation AI processors to ...
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$120K - $225K/yr
We're hiring experienced Design Verification Engineers from junior to senior levels to play a key role in developing and verifying the designs that will bring our next-generation AI processors to ...
Sunnyvale, CA · On-site
$161K - $197K/yr
Title - Design Verification Engineer -Performance Modelling Location - Sunnyvale CA, Austin TX or Remote Key Responsibilities * Develop, maintain, and enhance STL (Scenario/Test List) generation ...
New
Sunnyvale, CA · On-site
$161K - $197K/yr
Title - Design Verification Engineer -Performance Modelling Location - Sunnyvale CA, Austin TX or Remote Key Responsibilities * Develop, maintain, and enhance STL (Scenario/Test List) generation ...
New
Austin, TX · On-site
$120K - $225K/yr
We're hiring experienced Design Verification Engineers from junior to senior levels to play a key role in developing and verifying the designs that will bring our next-generation AI processors to ...
Austin, TX · On-site
$120K - $225K/yr
We're hiring experienced Design Verification Engineers from junior to senior levels to play a key role in developing and verifying the designs that will bring our next-generation AI processors to ...
Palo Alto, CA · On-site
$120K - $225K/yr
We're hiring experienced Design Verification Engineers from junior to senior levels to play a key role in developing and verifying the designs that will bring our next-generation AI processors to ...
Palo Alto, CA · On-site
$120K - $225K/yr
We're hiring experienced Design Verification Engineers from junior to senior levels to play a key role in developing and verifying the designs that will bring our next-generation AI processors to ...
Austin, TX · On-site
$134K - $164K/yr
Description As a Design Verification Engineer, you'll be at the center of our silicon design group's verification efforts, ensuring the quality and reliability of next-generation cellular systems.
Austin, TX · On-site
$134K - $164K/yr
Description As a Design Verification Engineer, you'll be at the center of our silicon design group's verification efforts, ensuring the quality and reliability of next-generation cellular systems.
Austin, TX · On-site
$134K - $164K/yr
Description As a Design Verification Engineer, you'll be at the center of our silicon design group's verification efforts, ensuring the quality and reliability of next-generation cellular systems.
Austin, TX · On-site
$134K - $164K/yr
Description As a Design Verification Engineer, you'll be at the center of our silicon design group's verification efforts, ensuring the quality and reliability of next-generation cellular systems.
Lebanon, IN · On-site
$130K - $159K/yr
Job Title: Sr. Design Verification Engineer Location: Remote Onsite Requirement: Approximately 1 week per month onsite at the project location in Lebanon, IN Duration: Longterm Job Summary The Sr. ...
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Lebanon, IN · On-site
$130K - $159K/yr
Job Title: Sr. Design Verification Engineer Location: Remote Onsite Requirement: Approximately 1 week per month onsite at the project location in Lebanon, IN Duration: Longterm Job Summary The Sr. ...
Austin, TX · On-site
$120K - $225K/yr
We're hiring experienced Design Verification Engineers from junior to senior levels to play a key role in developing and verifying the designs that will bring our next-generation AI processors to ...
Austin, TX · On-site
$120K - $225K/yr
We're hiring experienced Design Verification Engineers from junior to senior levels to play a key role in developing and verifying the designs that will bring our next-generation AI processors to ...
$120K - $225K/yr
We're hiring experienced Design Verification Engineers from junior to senior levels to play a key role in developing and verifying the designs that will bring our next-generation AI processors to ...
Quick apply
$120K - $225K/yr
We're hiring experienced Design Verification Engineers from junior to senior levels to play a key role in developing and verifying the designs that will bring our next-generation AI processors to ...
San Diego, CA · On-site
$144K - $176K/yr
Design Verification Engineer Duration: Full time or Contract Location: Bay Area, CA About Us: We are representing Sivaltech, A design services company headquartered in Milpitas, CA. We provide ...
San Diego, CA · On-site
$144K - $176K/yr
Design Verification Engineer Duration: Full time or Contract Location: Bay Area, CA About Us: We are representing Sivaltech, A design services company headquartered in Milpitas, CA. We provide ...
Plano, TX · On-site
$130K - $158K/yr
and other details - We are seeking an ASIC Design Verification Engineer whose role will be to verify the functionality, performance, and robustness of our custom silicon designs. You will help define ...
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Plano, TX · On-site
$130K - $158K/yr
and other details - We are seeking an ASIC Design Verification Engineer whose role will be to verify the functionality, performance, and robustness of our custom silicon designs. You will help define ...
Santa Clara, CA · On-site
$100K - $120K/yr
We are looking for a Design Verification Engineer to join our growing team in Fremont, CA United States! Essential Functions: * Lead verification activities and take ownership of deliverables ...
Santa Clara, CA · On-site
$100K - $120K/yr
We are looking for a Design Verification Engineer to join our growing team in Fremont, CA United States! Essential Functions: * Lead verification activities and take ownership of deliverables ...
$146K - $178K/yr
Design Verification Engineer Location: Santa Clara, CA Duration: 06 months (High Possibility of an extension) Senior DV engineer responsible for defining and implementing verification methodology and ...
$146K - $178K/yr
Design Verification Engineer Location: Santa Clara, CA Duration: 06 months (High Possibility of an extension) Senior DV engineer responsible for defining and implementing verification methodology and ...
$122K - $214K/yr
Description As a Design Verification Engineer, you'll be at the center of our silicon design group's verification efforts, ensuring the quality and reliability of next-generation cellular systems.
$122K - $214K/yr
Description As a Design Verification Engineer, you'll be at the center of our silicon design group's verification efforts, ensuring the quality and reliability of next-generation cellular systems.
$175K - $308K/yr
Description As a Design Verification Engineer, you'll be at the center of our silicon design group's verification efforts, ensuring the quality and reliability of next-generation cellular systems.
$175K - $308K/yr
Description As a Design Verification Engineer, you'll be at the center of our silicon design group's verification efforts, ensuring the quality and reliability of next-generation cellular systems.
$122K - $214K/yr
Description As a Design Verification Engineer, you'll be at the center of our silicon design group's verification efforts, ensuring the quality and reliability of next-generation cellular systems.
$122K - $214K/yr
Description As a Design Verification Engineer, you'll be at the center of our silicon design group's verification efforts, ensuring the quality and reliability of next-generation cellular systems.
Irvine, CA · On-site
$146K - $178K/yr
Design Verification Engineer Location: Santa Clara, CA Duration: 06 months (High Possibility of an extension) Senior DV engineer responsible for defining and implementing verification methodology and ...
Irvine, CA · On-site
$146K - $178K/yr
Design Verification Engineer Location: Santa Clara, CA Duration: 06 months (High Possibility of an extension) Senior DV engineer responsible for defining and implementing verification methodology and ...
$105.5K - $111.1K
0% of jobs
$111.1K - $116.7K
0% of jobs
$116.7K - $122.3K
0% of jobs
$122.3K - $127.9K
0% of jobs
$127.9K - $133.5K
0% of jobs
$135.6K is the 25th percentile. Wages below this are outliers.
$133.5K - $139K
65% of jobs
$139K - $144.6K
0% of jobs
$144.6K - $150.2K
0% of jobs
$150.2K - $155.8K
0% of jobs
$155.8K - $161.4K
0% of jobs
$163K is the 75th percentile. Wages above this are outliers.
$161.4K - $167K
35% of jobs
$105.5K
$149.2K
$167K
Design Verification Engineers require a solid background in digital design concepts, computer engineering, and electrical engineering, usually supported by a relevant bachelor’s or master’s degree. Expertise with hardware description languages like Verilog or VHDL, simulation tools, and familiarity with Unix/Linux environments are typical technical requirements, with certifications in FPGA/ASIC design considered advantageous. Strong analytical thinking, problem-solving skills, teamwork, and effective communication help these engineers collaborate closely with design, validation, and development teams. These competencies are vital to ensuring design correctness, catching flaws early, and driving efficient, reliable hardware development.
A Design Verification Engineer ensures that hardware designs function correctly by developing and executing test plans, writing verification code (often in SystemVerilog with UVM), and debugging design issues. They work closely with design and validation teams to confirm specifications are met before manufacturing. Their role is critical in preventing costly design flaws and ensuring high-quality semiconductor products.
Design Verification Engineers often face the challenge of thoroughly validating complex digital designs within tight project deadlines. Debugging intricate issues, dealing with evolving specifications, and ensuring complete coverage during simulation can require a great deal of attention to detail and persistence. Collaboration with designers, validation teams, and often cross-functional groups is critical to resolving ambiguities and preventing errors from reaching production. Adapting to new verification methodologies or tools is also common as technologies and standards advance. These challenges offer valuable learning opportunities and play a crucial role in producing robust, high-quality hardware products.
$144K - $176K/yr
Full-time
Re-posted 27 days ago
Mirafra is a global product engineering services company with expertise in semiconductor design, embedded and application software.
Job Title : Design Verification Engineer
Job Type : Full time
Location : San Diego And Bay Area
Job Description :
Strong verification skills: test planning, problem solving, debug,
adversarial testing. Multimedia Camera Image processing, Video or graphics
hardware experience is preferred.
Strong working knowledge of HVLs: System Verilog, VERA/e-Specman, System C.
Experience with methodologies like RVM/VMM/OVM/UVM. RTL design experience
and/or very strong OOPs programming experience is also a plus.
Good written and oral communications skills required.
Experience with simulation acceleration tool like Veloce/Palladium is a plus.
Skill required:
CPU, (MC: middle core, ARM architecture)
Decent knowledge of assertions.
SV and decent UVM knowledge
Code coverage.
Verilog or VHDL, C/C++, Tcl/Perl/shell-scripting.
All your information will be kept confidential according to EEO guidelines.
