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Design Verification Engineer Jobs (NOW HIRING)

Design Verification Engineer

San Diego, CA · On-site

$144K - $176K/yr

Design Verification Engineer Job Type : Full time Location : San Diego And Bay Area : Strong verification skills: test planning, problem solving, debug, adversarial testing. Multimedia Camera Image ...

Design verification engineer

San Diego, CA · Remote

$139K - $169K/yr

Design Verification Engineer Location: Remote anywhere in the USA and Canada Duration: Full-time (REMOTE) VISA: ONLY USC AND GC We are looking for humble geniuses, who believe that engineering has ...

Design Verification Engineer

Sunnyvale, CA · On-site

$159K - $194K/yr

Description We are looking for an experienced design verification engineer to join our SoC team at Baidu's Sunnyvale office. The successful candidate will be a motivated self-starter who will thrive ...

Senior Design Verification Engineer

Austin, TX · On-site

$134K - $164K/yr

  • Medical

  • Retirement

Senior Design Verification Engineer ID: 1061 Location: Austin, TX More about this job > Description Senior Design Verification Engineer Looking for new challenges? Would you like the variety of a ...

Design Verification Engineer

Santa Clara, CA · On-site

$159K - $195K/yr

We are seeking a skilled Design Verification Engineer to join our hardware engineering team. The ideal candidate will be responsible for verifying complex digital designs using advanced verification ...

We're hiring experienced Design Verification Engineers from junior to senior levels to play a key role in developing and verifying the designs that will bring our next-generation AI processors to ...

We're hiring experienced Design Verification Engineers from junior to senior levels to play a key role in developing and verifying the designs that will bring our next-generation AI processors to ...

We're hiring experienced Design Verification Engineers from junior to senior levels to play a key role in developing and verifying the designs that will bring our next-generation AI processors to ...

As a Design Verification Engineer, you will work across the full verification cycle - from developing detailed verification plans and building test benches through running coverage regressions ...

Senior Design Verification Engineer

Austin, TX

$134K - $164K/yr

  • Medical

  • Retirement

Senior Design Verification Engineer ID: 1064 Location: Austin, TX More about this job > Description Senior Design Verification Engineer Looking for new challenges? Would you like the variety of a ...

Design Verification Engineer

Austin, TX · On-site

$134K - $164K/yr

Description As a Design Verification Engineer, you'll be at the center of our silicon design group's verification efforts, ensuring the quality and reliability of next-generation cellular systems.

We're hiring experienced Design Verification Engineers from junior to senior levels to play a key role in developing and verifying the designs that will bring our next-generation AI processors to ...

Design Verification Engineer

Knoxville, TN · On-site

$129K - $158K/yr

As a Design Verification Engineer, you will work across the full verification cycle - from developing detailed verification plans and building test benches through running coverage regressions ...

We're hiring experienced Design Verification Engineers from junior to senior levels to play a key role in developing and verifying the designs that will bring our next-generation AI processors to ...

Design Verification Engineer

Broomfield, CO · On-site

$108 - $172.80/hr

  • Medical

  • Dental

  • Vision

  • Retirement

  • PTO

Design Verification Engineer Broadcom's ASIC Products Division (APD) is looking for an experienced verification engineer responsible for modeling and verification activities for complex digital and ...

Design Verification Engineer

Dallas, TX · On-site

$135K - $164K/yr

Fiori Technology Solutions is currently hiring for a Design Verification Engineer. This is fulltime permanent position. We are looking to fill multiple Design Verification openings. We are ...

Design Verification Engineer

Chicago, IL · On-site

$45 - $55/hr

  • Medical

  • Dental

  • Retirement

  • PTO

Our client is seeking an experienced Design Verification Engineer to lead the planning, development, and execution of verification activities for medical device products. This individual will serve ...

Showing results 21-40

Design Verification Engineer information

See salary details

$105.5K

$149.2K

$167K

How much do design verification engineer jobs pay per year?

As of Aug 18, 2026, the average yearly pay for design verification engineer in the United States is $149,150.00, according to ZipRecruiter salary data. Most workers in this role earn between $136,000.00 and $166,000.00 per year, depending on experience, location, and employer.

What is a design verification engineer?

A Design Verification Engineer ensures that hardware designs function correctly by developing and executing test plans, writing verification code (often in SystemVerilog with UVM), and debugging design issues. They work closely with design and validation teams to confirm specifications are met before manufacturing. Their role is critical in preventing costly design flaws and ensuring high-quality semiconductor products.

What skills and qualifications are needed to be a design verification engineer?

Design Verification Engineers require a solid background in digital design concepts, computer engineering, and electrical engineering, usually supported by a relevant bachelor’s or master’s degree. Expertise with hardware description languages like Verilog or VHDL, simulation tools, and familiarity with Unix/Linux environments are typical technical requirements, with certifications in FPGA/ASIC design considered advantageous. Strong analytical thinking, problem-solving skills, teamwork, and effective communication help these engineers collaborate closely with design, validation, and development teams. These competencies are vital to ensuring design correctness, catching flaws early, and driving efficient, reliable hardware development.

What are the most common challenges faced by design verification engineers in their daily work?

Design Verification Engineers often face the challenge of thoroughly validating complex digital designs within tight project deadlines. Debugging intricate issues, dealing with evolving specifications, and ensuring complete coverage during simulation can require a great deal of attention to detail and persistence. Collaboration with designers, validation teams, and often cross-functional groups is critical to resolving ambiguities and preventing errors from reaching production. Adapting to new verification methodologies or tools is also common as technologies and standards advance. These challenges offer valuable learning opportunities and play a crucial role in producing robust, high-quality hardware products.

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Infographic showing various Design Verification Engineer job openings in the United States as of August 2026, with employment types broken down into 89% Full Time, 7% Part Time, and 4% Contract. Highlights an 83% Physical, 5% Hybrid, and 12% Remote job distribution, with an average salary of $149,150 per year, or $71.7 per hour.

Design Verification Engineer

Mirafra Technology

San Diego, CA • On-site

$144K - $176K/yr

Full-time

Re-posted 8 days ago


Job description

Company Description

Mirafra is a global product engineering services company with expertise in semiconductor design, embedded and application software.

Job Description

Job Title : Design Verification Engineer

Job Type : Full time

Location : San Diego And Bay Area

Job Description :
Strong verification skills: test planning, problem solving, debug,
adversarial testing. Multimedia Camera Image processing, Video or graphics
hardware experience is preferred.
Strong working knowledge of HVLs: System Verilog, VERA/e-Specman, System C.
Experience with methodologies like RVM/VMM/OVM/UVM. RTL design experience
and/or very strong OOPs programming experience is also a plus.
Good written and oral communications skills required.
Experience with simulation acceleration tool like Veloce/Palladium is a plus.
Skill required:
CPU, (MC: middle core, ARM architecture)
Decent knowledge of assertions.
SV and decent UVM knowledge
Code coverage.
Verilog or VHDL, C/C++, Tcl/Perl/shell-scripting.

Additional Information

All your information will be kept confidential according to EEO guidelines.