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Design Verification Engineer Jobs in Wisconsin (NOW HIRING)

The Engineer II, Systems Verification uses a technical background in software development and ... Design testing strategies and detailed test plans for functional verification of complex systems at ...

Plan and execute design verification & validation testing, ensuring performance, safety, and regulatory compliance * Analyze test data and present clear engineering recommendations to project leaders ...

Sr Design Engineer, Motors

Brookfield, WI · On-site

$98.90K - $135.80K/yr

Senior Design Engineer, Motors INNOVATE WITHOUT BOUNDARIES! At Milwaukee Tool we firmly believe ... to verify motor performance and thermal limits per project requirements. You will identify ...

Sr Design Engineer, Motors

Brookfield, WI · On-site

$98.90K - $135.80K/yr

Senior Design Engineer, Motors INNOVATE WITHOUT BOUNDARIES! At Milwaukee Tool we firmly believe ... to verify motor performance and thermal limits per project requirements. You will identify ...

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Design Verification Engineer information

See Wisconsin salary details

$106.5K

$150.5K

$168.6K

How much do design verification engineer jobs pay per year?

As of May 28, 2026, the average yearly pay for design verification engineer in Wisconsin is $150,545.00, according to ZipRecruiter salary data. Most workers in this role earn between $137,300.00 and $167,600.00 per year, depending on experience, location, and employer.

What is a Design Verification Engineer job?

A Design Verification Engineer ensures that hardware designs function correctly by developing and executing test plans, writing verification code (often in SystemVerilog with UVM), and debugging design issues. They work closely with design and validation teams to confirm specifications are met before manufacturing. Their role is critical in preventing costly design flaws and ensuring high-quality semiconductor products.

What are the key skills and qualifications needed to thrive in the Design Verification Engineer position, and why are they important?

Design Verification Engineers require a solid background in digital design concepts, computer engineering, and electrical engineering, usually supported by a relevant bachelor’s or master’s degree. Expertise with hardware description languages like Verilog or VHDL, simulation tools, and familiarity with Unix/Linux environments are typical technical requirements, with certifications in FPGA/ASIC design considered advantageous. Strong analytical thinking, problem-solving skills, teamwork, and effective communication help these engineers collaborate closely with design, validation, and development teams. These competencies are vital to ensuring design correctness, catching flaws early, and driving efficient, reliable hardware development.

What are the most common challenges faced by Design Verification Engineers in their daily work?

Design Verification Engineers often face the challenge of thoroughly validating complex digital designs within tight project deadlines. Debugging intricate issues, dealing with evolving specifications, and ensuring complete coverage during simulation can require a great deal of attention to detail and persistence. Collaboration with designers, validation teams, and often cross-functional groups is critical to resolving ambiguities and preventing errors from reaching production. Adapting to new verification methodologies or tools is also common as technologies and standards advance. These challenges offer valuable learning opportunities and play a crucial role in producing robust, high-quality hardware products.
What are the most commonly searched types of Design Verification Engineer jobs in Wisconsin? The most popular types of Design Verification Engineer jobs in Wisconsin are:
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What cities in Wisconsin are hiring for Design Verification Engineer jobs? Cities in Wisconsin with the most Design Verification Engineer job openings:
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Infographic showing various Design Verification Engineer job openings in Wisconsin as of May 2026, with employment types broken down into 85% Full Time, 11% Part Time, and 4% Contract. Highlights an 81% Physical, 2% Hybrid, and 17% Remote job distribution, with an average salary of $150,545 per year, or $72.4 per hour.

VLSI Design Verification Manager - Slingshot ASIC Team

Hewlett Packard Enterprise Development LP

Chippewa Falls, WI

Full-time

Posted 14 days ago


Job description

VLSI Design Verification Manager - Slingshot ASIC TeamThis role has been designed as ''Onsite' with an expectation that you will primarily work from an HPE office.

Who We Are:

Hewlett Packard Enterprise is the global edge-to-cloud company advancing the way people live and work. We help companies connect, protect, analyze, and act on their data and applications wherever they live, from edge to cloud, so they can turn insights into outcomes at the speed required to thrive in today's complex world.Our culture thrives onfinding new and better ways to accelerate what's next.We know varied backgrounds are valued and succeed here. We have the flexibility to manage our work and personal needs.We make bold moves, together, and are a force for good. If you are looking to stretch and grow your career our culture will embrace you.Open up opportunities with HPE.

Job Description:

Job Description
Hewlett Packard Enterprise is seeking aVLSI Design Verification Managerto lead design verification forSlingshot networking ASICs, the highperformance interconnect used in HPE's flagship HPC and AI supercomputers. HPE Slingshot is a modern, Ethernetbased interconnect purposebuilt for largescale HPC and AI clusters, delivering industryleading bandwidth, low latency, adaptive routing and scalability for demanding workloads. In this role, you will lead a team of design verification engineers responsible for ensuring functional correctness and quality of complex networking ASICs used in NIC and switch products. You will own verification methodology, execution quality, and signoff readiness, while growing and mentoring engineers across a range of experience levels.
This role manages a team of approximately8-15 engineers(TCP01-TCP05)and sits at the intersection of deep technical leadership, people development, and program execution.

Responsibilities

  • Provide leadership and direction for a team responsible for all phases ofpresilicon design verification, including verification planning, testbench development, coverage closure, regression management, and signoff reviews.
  • Define, own, and evolvedesign verification methodology, ensuring consistent, highquality verification practices across block, subsystem, and fullchip scopes.
  • Ensure development of robustSystemVerilog/UVMbased environments, including stimulus, scoreboards, checkers, assertions, and functional coverage.
  • Drive regression health, failure triage, rootcause isolation, and closure of design issues in close collaboration with logic design and architecture teams.
  • Manage project deliverables, schedules, and staffing to meet program milestones and quality goals.
  • Recruit, mentor, and develop engineers; set performance expectations and support career growth across junior through senior levels.
  • Identify and drive opportunities for process improvement, reuse, automation, and efficiency in verification workflows.
  • Communicate verification status, risks, and readiness clearly to management and crossfunctional partners.
Education and Experience Required
  • Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or equivalent.
  • Typically10+ years of experience in VLSI design verification, with strong handson background in presilicon DV.
Required Knowledge and Skills
  • Strong understanding ofSystemVerilog and UVMbased verification methodologies.
  • Demonstratedtechnical leadershipin design verification. (e.g., DV technical lead, block or project verification owner)
  • Ability to lead engineers through influence, technical credibility, mentorship, and clear communication.
  • Experience with verification planning, coveragedriven verification, regression management, and signoff readiness.
  • Proficiency with DV workflows using industry EDA simulation tools.
  • Strong analytical and problemsolving skills.
  • Excellent written and verbal communication skills.
  • Ability to operate effectively in a multisite, crossfunctional engineering environment.
Preferred Knowledge and Skills
  • Previous peoplemanagement experience, including hiring, coaching, and performance management.
  • Direct experience withSynopsys VCSlargescale regression execution, triage workflows, and performance/throughput optimization.
  • Familiarity with GitHub Enterprise Cloud development workflows and AI tools is a plus.
  • Familiarity with highperformance networking, Ethernet, SERDES, PCIe, or HPC/AI systems is a plus.
  • Experience improving verification efficiency through automation, reuse, or methodology refinement.

What We Can Offer You:

Health & Wellbeing

We strive to provide our team members and their loved ones with a comprehensive suite of benefits that supports their physical, financial and emotional wellbeing.

Personal & Professional Development

We also invest in your career because the better you are, the better we all are. We have specific programs catered to helping you reach any career goals you have - whether you want to become a knowledge expert in your field or apply your skills to another division.

Unconditional Inclusion

We are unconditionally inclusive in the way we work and celebrate individual uniqueness. We know varied backgrounds are valued and succeed here. We have the flexibility to manage our work and personal needs. We make bold moves, together, and are a force for good.

Let's Stay Connected:

Follow @HPECareers on Instagram to see the latest on people, culture and tech at HPE.

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Job:

Engineering

Job Level:

Manager_1"The expected salary/wage range for this position is provided below. Actual offer may vary from this range based upon geographic location, work experience, education/training, and/or skill level.
- United States of America: Annual Salary USD 142,000 - 270,000 in Colorado // 135,000 - 310,500 in Minnesota & Wisconsin
The listed salary range reflects base salary. Variable incentives may also be offered."

Information about employee benefits offered in the US can be found at https://myhperewards.com/main/new-hire-enrollment.html

The estimated job application period closure is May 15 2026; this timeline is provided for transparency and internal planning purposes.

HPE is an Equal Employment Opportunity/ Veterans/Disabled/LGBT employer. We do not discriminate on the basis of race, gender, or any other protected category, and all decisions we make are made on the basis of qualifications, merit, and business need. Our goal is to be one global team that is representative of our customers, in an inclusive environment where we can continue to innovate and grow together. Please click here: Equal Employment Opportunity.

Hewlett Packard Enterprise is EEO Protected Veteran/ Individual with Disabilities.

HPE will comply with all applicable laws related to employer use of arrest and conviction records, including laws requiring employers to consider for employment qualified applicants with criminal histories.

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Please note that Hewlett Packard Enterprise (HPE), its direct and indirect subsidiaries and affiliated companies, and its authorized recruitment agencies/vendorswill never charge any candidate a registration fee, hiring fee, or any other fee in connection with its recruitment and hiring process.The credentials of any hiring agency that claims to be working with HPE for recruitment of talent should be verified by candidates and candidates shall be solely responsible to conduct such verification. Any candidate/individual who relies on the erroneous representations made by fraudulent employment agencies does so at their own risk, and HPE disclaims liability for any damages or claims that may result from any such communication.