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Formal Verification Jobs (NOW HIRING)

Distinguished Formal Verification

San Jose, CA ยท On-site

$230K - $285K/yr

Astera Labs is seeking a Distinguished Engineer, Formal Verification to join our world-class engineering team in San Jose, California. As a hyper-growth leader in AI infrastructure connectivity, w ...

Work with the best Formal Verification team in the world and acquire experience being at the center of a System-on-a-chip (SoC) design verification effort collaborating with design. Are you ...

Learn from the best Formal Verification team in the world and acquire experience being at the center of a System-on-a-chip (SoC) design verification effort collaborating with design. Are you ...

Distinguished Formal Verification

San Jose, CA ยท On-site

$159K/yr

Astera Labs is seeking a Distinguished Engineer, Formal Verification to join our world-class engineering team in San Jose, California. As a hyper-growth leader in AI infrastructure connectivity, w ...

You will drive formal verification across the custom IP, interface IP, and SoC subsystems that power our ASICs, including compute arrays, DMA engines, NoCs, memory systems, PCIe, Ethernet, CPU ...

Learn from the best Formal Verification team in the world and acquire experience being at the center of a System-on-a-chip (SoC) design verification effort collaborating with design. Are you ...

Learn from the best Formal Verification team in the world and acquire experience being at the center of a System-on-a-chip (SoC) design verification effort collaborating with design. Are you ...

Work with the best Formal Verification team in the world and acquire experience being at the center of a System-on-a-chip (SoC) design verification effort collaborating with design. Are you ...

Formal Verification Engineer

Austin, TX ยท On-site

$134K/yr

Learn from the best Formal Verification team in the world and acquire experience being at the center of a System-on-a-chip (SoC) design verification effort collaborating with design. Are you ...

You will drive formal verification across the custom IP, interface IP, and SoC subsystems that power our ASICs, including compute arrays, DMA engines, NoCs, memory systems, PCIe, Ethernet, CPU ...

Learn from the best Formal Verification team in the world and acquire experience being at the center of a System-on-a-chip (SoC) design verification effort collaborating with design. Are you ...

Formal Verification Engineer

Austin, TX ยท On-site

$134K/yr

Learn from the best Formal Verification team in the world and acquire experience being at the center of a System-on-a-chip (SoC) design verification effort collaborating with design. Are you ...

Formal Verification Engineer

Austin, TX ยท On-site

$134K/yr

Work with the best Formal Verification team in the world and acquire experience being at the center of a System-on-a-chip (SoC) design verification effort collaborating with design. Are you ...

Learn from the best Formal Verification team in the world and acquire experience being at the center of a System-on-a-chip (SoC) design verification effort collaborating with design. Are you ...

Work with the best Formal Verification team in the world and acquire experience being at the center of a System-on-a-chip (SoC) design verification effort collaborating with design. Are you ...

DV Formal Verification

Mountain View, CA ยท On-site

$200K - $420K/yr

About the role Own block- and SOC-level formal verification, debug, and proof convergence for our AI accelerator silicon. Work with chip-design and software teams driving DensityAI's AI accelerator ...

About the role Own block- and SOC-level formal verification, debug, and proof convergence for our AI accelerator silicon. Work with chip-design and software teams driving DensityAI's AI accelerator ...

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How much do formal verification jobs pay per hour?

As of Jul 21, 2026, the average hourly pay for formal verification in the United States is $20.70, according to ZipRecruiter salary data. Most workers in this role earn between $15.38 and $21.88 per hour, depending on experience, location, and employer.

What is a Formal Verification job?

A Formal Verification job involves using mathematical techniques to prove the correctness of hardware or software designs. Engineers in this role apply formal methods, such as model checking and theorem proving, to ensure that a system behaves as intended without relying solely on traditional testing. This process helps detect critical design flaws early, improving reliability and reducing costly errors. Formal verification is widely used in safety-critical industries like aerospace, automotive, and semiconductor design.

What are the key skills and qualifications needed to thrive in the Formal Verification position, and why are they important?

To thrive in Formal Verification, you need a strong background in computer science, mathematics, and logical reasoning, often supported by a relevant degree in engineering or computer science. Familiarity with formal verification tools such as ModelSim, JasperGold, SystemVerilog Assertions, and proficiency in hardware description languages like Verilog or VHDL are important, and industry certifications can be a plus. Excellent analytical thinking, attention to detail, and strong communication skills help in interpreting specifications and collaborating with cross-functional teams. These skills are crucial to rigorously ensuring hardware or software designs function correctly and meet industry safety and correctness standards.

What are the typical daily responsibilities of a Formal Verification engineer?

A Formal Verification engineer's daily responsibilities usually include developing and applying formal models to hardware or software designs, writing assertions, and using verification tools to prove or disprove correctness properties. Collaboration with design, simulation, and verification teams is common to clarify specifications and address any verification gaps. Engineers frequently analyze failures or counterexamples, document findings, and suggest design improvements. This role often involves balancing multiple projects, staying aligned with tight development schedules, and ensuring the highest possible design quality before production.

More about Formal Verification jobs
What cities are hiring for Formal Verification jobs? Cities with the most Formal Verification job openings:
What are the most commonly searched types of Formal Verification jobs? The most popular types of Formal Verification jobs are:
What states have the most Formal Verification jobs? States with the most job openings for Formal Verification jobs include:
Infographic showing various Formal Verification job openings in the United States as of July 2026, with employment types broken down into 90% Full Time, 9% Part Time, and 1% Contract. Highlights an 94% Physical, 1% Hybrid, and 5% Remote job distribution, with an average salary of $43,051 per year, or $20.7 per hour.

Formal Verification Engineer

SWITS DIGITAL Private Limited

San Jose, CA โ€ข On-site

$159K/yr

Full-time

This job post hasย expired today.ย Applications are no longer accepted.


Job description

Job Title: Formal Verification Engineer
Location: San Jose, CA - Full Time
Job Description:
We are looking for formal verification experts to ensure design correctness using mathematical verification techniques and advanced formal tools.
Key Responsibilities:
  • Develop formal verification strategies and methodologies
  • Write System Verilog Assertions (SVA)
  • Perform property checking, equivalence checking, and CDC/RDC analysis
  • Identify corner cases missed in simulation
  • Collaborate with RTL teams for design improvements

Required Skills:
  • Strong knowledge of formal verification tools (Jasper, VC Formal, etc.)
  • Expertise in SVA and property specification
  • Solid understanding of digital design and logic reasoning

Good to Have:
  • Experience in low-power/CDC verification
  • Exposure to security verification