ZipRecruiter

Log In

1

Uvm Verification Jobs (NOW HIRING)

Airspan

UVM SYSTEMVERILOG VERIFICATION ENGINEER

Warren, NJ · On-site

$141K/yr

Airspan Careers UVM SYSTEMVERILOG VERIFICATION ENGINEER Location: Warren, New Jersey, Plano, TX or REMOTE U.S. Company: AirSpan Networks About AirSpan AirSpan Networks is a global provider of ...

Saransh Inc

FPGA Verification Engineer

Mountain View, CA · On-site

$153K - $197K/yr

Proficiency in System Verilog and UVM verification methodology * Experience in FPGA verification Key Responsibilities: * Develop and execute comprehensive verification plans for FPGA designs.

Pic-Time Ltd.

Verification Engineer

Denver, CO · On-site

$130 - $200/hr

Plan & implement UVM verification environments developing tests, testbenches, UVM components, and regressions/test lists * Responsible for generating and executing the Verification Test Plan and ...

New

Correct Designs

Design Verification Engineer

Austin, TX · On-site

$134K - $164K/yr

Correct Designs is currently seeking talented Verification Engineers with prior System Verilog UVM experience to work with our major clients both in Austin, TX, and nationwide. Opportunities span ...

Correct Designs

Design Verification Engineer

Austin, TX · On-site

$134K - $164K/yr

Correct Designs is currently seeking talented Verification Engineers with prior System Verilog UVM experience to work with our major clients both in Austin, TX, and nationwide. Opportunities span ...

Embtel Inc

Design Verification Engineer (Remote)

Sunnyvale, CA · On-site

$159K - $194K/yr

Design Verification Engineer Locations : Sunnyvale, CA (Remote) No. of positions: 09 Duration: 6+ ... Building a test bench for a block using System Verilog and UVM Writing random tests, directed tests ...

Correct Designs

Design Verification Engineer

Austin, TX

$134K - $164K/yr

Correct Designs is currently seeking talented Verification Engineers with prior System Verilog UVM experience to work with our major clients both in Austin, TX, and nationwide. Opportunities span ...

Correct Designs

Design Verification Engineer

Austin, TX

$134K - $164K/yr

Correct Designs is currently seeking talented Verification Engineers with prior System Verilog UVM experience to work with our major clients both in Austin, TX, and nationwide. Opportunities span ...

SambaNova

Design Verification Engineer

San Jose, CA · On-site

$159K - $194K/yr

You'll build SystemVerilog and UVM verification environments alongside architects, RTL designers, and firmware engineers, and take ownership of verification plans from first draft through closure.

New

Epitec

Design Verification Engineer III

Sunnyvale, CA · On-site

$159K - $194K/yr

Design Verification Engineer III Contract Duration: 6 months, possible extension Location ... Build and maintain SystemVerilog/UVM testbenches; write directed and constrained-random tests.

next page

Showing results 1-20

All JobsBusiness JobsHuman Resources JobsHuman Resources Specialist JobsUvm Verification Jobs

Uvm Verification information

See salary details

$80K

$142.6K

$203.5K

How much do uvm verification jobs pay per year?

As of Aug 21, 2026, the average yearly pay for uvm verification in the United States is $142,619.00, according to ZipRecruiter salary data. Most workers in this role earn between $136,000.00 and $136,000.00 per year, depending on experience, location, and employer.

What is a UVM Verification?

A UVM Verification job involves verifying the functionality of digital hardware designs using the Universal Verification Methodology (UVM). Engineers in this role create testbenches, write SystemVerilog code, and develop constrained-random and directed tests to validate chip designs. They work closely with design teams to find and debug issues before fabrication, ensuring high-quality and reliable silicon. UVM verification is essential in industries like semiconductors, automotive, and communications to meet performance and reliability standards.

What are the typical day-to-day responsibilities of a UVM Verification engineer?

As a UVM Verification engineer, your day-to-day tasks generally include developing test benches, writing and executing test cases, analyzing simulation results, and debugging issues using UVM methodologies. You'll collaborate closely with design engineers to understand specifications and verify that the hardware operates as intended, and you may also contribute to code reviews and continuous integration processes. In addition to technical development, regular meetings for planning, status updates, and issue resolution are common. This role offers opportunities to mentor junior team members and stay up to date with the latest verification techniques and tools, fostering both team and personal growth.

What are the key skills and qualifications needed to thrive in the UVM Verification position, and why are they important?

To thrive as a UVM Verification engineer, you need a solid background in digital design fundamentals, SystemVerilog, and deep expertise in the Universal Verification Methodology (UVM), often backed by a degree in Electrical or Computer Engineering. Familiarity with simulation tools such as Mentor Questa or Synopsys VCS, as well as version control systems and UVM-specific certifications, is highly valuable. Strong analytical abilities, attention to detail, teamwork, and effective communication are important soft skills in this field. These competencies ensure robust, efficient verification of complex hardware designs, leading to higher product quality and successful project outcomes.

More about Uvm Verification jobs

What cities are hiring for Uvm Verification jobs?

Cities with the most Uvm Verification job openings:

What are the most commonly searched types of Uvm Verification jobs?

The most popular types of Uvm Verification jobs are:

What states have the most Uvm Verification jobs?

States with the most job openings for Uvm Verification jobs include:

What job categories do people searching Uvm Verification jobs look for?

The top searched job categories for Uvm Verification jobs are:

Uvm Verification jobs near you
Infographic showing various Uvm Verification job openings in the United States as of August 2026, with employment types broken down into 1% As Needed, 81% Full Time, 14% Part Time, 3% Contract, and 1% Nights. Highlights an 89% Physical, 3% Hybrid, and 8% Remote job distribution, with an average salary of $142,619 per year, or $68.6 per hour.

UVM SYSTEMVERILOG VERIFICATION ENGINEER

AIRSPAN CAREERS

Plano, TX • On-site

$100 - $140/hr

Other

Posted 3 days ago

New

Job description

Location: Warren, New Jersey, Plano, TX or REMOTE U.S.

Company: AirSpan Networks

About AirSpan

AirSpan Networks is a global provider of innovative 4G and 5G network solutions, enabling efficient and cost-effective connectivity for operators, enterprises, and industrial applications. We are looking for a skilled UVM SystemVerilog Verification Engineer to join our dynamic team and contribute to the validation and testing of our cutting‑edge communication technologies.

Job Description

As a UVM Verification Engineer, you will be responsible for developing and executing test plans using Universal Verification Methodology (UVM) to validate the functionality, performance, and reliability of AirSpan’s ASIC and FPGA designs. You will work closely with design and development teams to ensure compliance with specifications and industry standards.

Key Responsibilities
  • Develop and implement UVM‑based verification plans and test strategies for FPGA designs.
  • Perform functional, system‑level, and regression testing for digital hardware components.
  • Create test benches, test cases, and automation frameworks in System Verilog.
  • Analyze test results, debug issues, and collaborate with design teams to resolve defects.
  • Ensure compliance with industry standards and customer requirements.
  • Provide documentation and reports on test procedures, results, and defect tracking.
  • Continuously optimize test processes and tools to improve efficiency and accuracy.
Qualifications & Experience
  • Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related fields.
  • 10 years of experience in UVM‑based verification of FPGA systems.
  • Strong understanding of SystemVerilog and Universal Verification Methodology (UVM).
  • Proficiency in scripting languages such as Python or Perl for automation.
  • Experience with simulation tools such as ModelSim or QuestaSim.
  • Experience with C/C++.
  • Experience in implementing Bit Accurate Models and debugging DSP designs.
  • Familiarity with debugging tools, coverage metrics, and formal verification techniques.
  • Strong problem‑solving and analytical skills with attention to detail.
  • Knowledge of O‑RAN architecture and protocols for 4G and 5G networks.
  • Ability to work collaboratively in a fast‑paced, cross‑functional team environment.
Preferred Skills
  • Experience in verification of communication protocols.
  • Knowledge of FPGA development and hardware description languages such as VHDL/Verilog.
  • Understanding of hardware/software co‑verification techniques.
#J-18808-Ljbffr

Apply