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Part Time Uvm Verification Jobs (NOW HIRING)

Weekday AI

ASIC/SoC Design & Verification Engineer

$70 - $100/hr

This is a fully remote, part-time engagement requiring approximately 20-40 hours per week ... Functional Verification (UVM, SVA, Cocotb, testbench development) * IP Integration and SoC Bring-up ...

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Part Time Uvm Verification information

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$80K

$142.6K

$203.5K

How much do part time uvm verification jobs pay per year?

As of Aug 12, 2026, the average yearly pay for part time uvm verification in the United States is $142,619.00, according to ZipRecruiter salary data. Most workers in this role earn between $136,000.00 and $136,000.00 per year, depending on experience, location, and employer.

What are the key skills and qualifications needed to thrive as a part time UVM verification engineer?

To thrive as a Part Time UVM Verification Engineer, you need a solid background in digital design, SystemVerilog, and Universal Verification Methodology (UVM), often supported by a degree in electrical or computer engineering. Proficiency with simulation tools like Synopsys VCS, Cadence Incisive, and version control systems is typically required. Attention to detail, problem-solving ability, and effective teamwork are standout soft skills in this role. These competencies ensure the delivery of reliable, high-quality verification environments that are essential for successful hardware design projects.

What is a part time UVM verification job?

Part-time UVM verification jobs involve using the Universal Verification Methodology (UVM) to test and validate hardware designs, typically System-on-Chip (SoC) or ASICs, on a part-time basis. Professionals in these roles create testbenches, write verification components, and run simulations to ensure that digital circuits function correctly. This type of position is ideal for those who have experience in hardware verification but require flexible work hours, such as students, freelancers, or individuals balancing other commitments. Essential skills include knowledge of SystemVerilog, UVM methodology, and experience with simulation tools.

What is the difference between Part Time Uvm Verification vs Part Time Uvm Design?

AspectPart Time Uvm VerificationPart Time Uvm Design
Primary RoleVerifying UVM testbenches and ensuring functional correctnessCreating and developing UVM testbench components and environments
Skills & CertificationsUVM methodology, SystemVerilog, verification toolsUVM methodology, SystemVerilog, design tools
Work EnvironmentVerification labs, design teams, collaborative testing environmentsDesign teams, simulation environments, development labs
Industry UsageCommonly used in verification phases of chip designUsed during the design phase to build test environments

Part Time Uvm Verification focuses on testing and validating design correctness, while Part Time Uvm Design involves creating the testbench infrastructure. Both roles require UVM and SystemVerilog skills but serve different stages in the chip development process.

How do part time UVM verification engineers typically collaborate with full-time team members during project cycles?

Part-time UVM Verification engineers often work closely with full-time verification and design teams by participating in regular stand-up meetings, code reviews, and design discussions through remote collaboration tools. They are usually assigned specific verification tasks, testbench components, or regression runs that fit their availability, while maintaining clear documentation and communication to ensure continuity. While flexibility is a perk, effective collaboration requires proactive coordination to align work schedules, clarify expectations, and provide timely updates on progress or blockers. This structure helps integrate part-time contributors without compromising project timelines or quality.
More about Part Time Uvm Verification jobs
What are the most commonly searched types of Uvm Verification jobs? The most popular types of Uvm Verification jobs are:
What job categories do people searching Part Time Uvm Verification jobs look for? The top searched job categories for Part Time Uvm Verification jobs are:
Part Time Uvm Verification jobs near you
Infographic showing various Part Time Uvm Verification job openings in the United States as of August 2026, with employment types broken down into 1% As Needed, 79% Full Time, 15% Part Time, 4% Contract, and 1% Nights. Highlights an 90% Physical, 3% Hybrid, and 7% Remote job distribution, with an average salary of $142,619 per year, or $68.6 per hour.

ASIC/SoC Design & Verification Engineer

Weekday AI

Remote

$70 - $100/hr

Part-time

Posted 14 days ago

Job description

This role is for one of our clients
Compensation: $70-$100 per hour
Join a cutting-edge AI initiative focused on advancing how next-generation AI systems understand real-world hardware engineering. We are seeking experienced ASIC and SoC Design & Verification Engineers to contribute their expertise in digital design, RTL development, functional verification, and silicon implementation to improve AI model capabilities.
Whether you're an early-career engineer, a PhD researcher, or a seasoned professional who has successfully taken chips through tapeout, this opportunity allows you to apply your practical engineering knowledge to help train and evaluate frontier AI systems.
This is a fully remote, part-time engagement requiring approximately 20-40 hours per week, depending on your availability.
Requirements
Key Responsibilities
  • Design realistic chip architecture, RTL, debugging, and verification challenges based on real engineering experience.
  • Develop complete reference solutions, including RTL implementations, verification environments, testbenches, and supporting documentation using Verilog/SystemVerilog.
  • Evaluate AI-generated hardware solutions, identify strengths and weaknesses, and provide detailed technical feedback.
  • Analyze where AI models struggle with hardware engineering concepts, debugging, verification strategies, and design trade-offs.
  • Collaborate with fellow hardware engineers to maintain consistency, technical accuracy, and high-quality engineering standards across all evaluation tasks.
  • Help improve AI understanding of modern digital design methodologies, verification practices, and semiconductor development workflows.
Required Qualifications
  • Hands-on experience in ASIC and/or SoC design, functional verification, or digital hardware development, preferably involving production silicon or tapeout projects.
  • Strong proficiency in SystemVerilog and Verilog.
  • Experience working with industry-standard EDA tools such as Synopsys VCS, Cadence Xcelium, Siemens Questa, VC Formal, Verdi, or equivalent open-source tools including Icarus Verilog, Verilator, Cocotb, Yosys, and OpenROAD.
  • Strong understanding of system-level hardware concepts including interface protocols, clock-domain crossing (CDC), handshaking, backpressure, and multi-module data flow.
  • Deep expertise in one or more of the following areas:
    • RTL Design and Microarchitecture
    • Functional Verification (UVM, SVA, Cocotb, testbench development)
    • IP Integration and SoC Bring-up (AXI, PCIe, DDR, NoC, ARM-based systems)
    • Formal Verification and Coverage Closure
    • Timing Closure, Synthesis, Power, Performance, and Area (PPA) Optimization
    • Analog/Mixed-Signal Design Verification
    • Hardware Specification Development and Technical Documentation
  • Ability to commit 20-40 hours per week with reliable weekday availability.
  • Strong written communication skills and the ability to work independently in a remote environment.
Preferred Qualifications
  • Experience participating in AI model training, evaluation, data annotation, or technical benchmarking projects.
  • Graduate research or industry experience in semiconductor design, verification, or computer architecture.
  • Familiarity with modern AI-assisted engineering tools and automated hardware design workflows.
  • Experience mentoring engineers or reviewing complex technical designs.
Why Join
  • Help shape how advanced AI systems understand and solve real-world semiconductor engineering challenges.
  • Apply your practical chip design and verification expertise to improve the next generation of AI models.
  • Work alongside experienced hardware engineers, researchers, and AI specialists on high-impact projects.
  • Enjoy the flexibility of a fully remote engagement with opportunities for continued collaboration based on performance.
Equal Opportunity
We are committed to creating an inclusive environment and welcome applications from qualified professionals of all backgrounds. Reasonable accommodations are available throughout the application and engagement process.
Contract & Engagement Details
  • Independent contractor engagement.
  • Fully remote with flexible working hours.
  • Expected commitment of approximately 20-40 hours per week.
  • Project duration may be extended, shortened, or concluded based on project requirements and individual performance.
  • Work does not require access to confidential or proprietary information from any current or former employer.
  • Payments are issued weekly based on approved work completed.
  • At this time, we are unable to support H1-B or STEM OPT candidates.

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