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Intern Uvm Verification Jobs (NOW HIRING)

Etched

DV Intern

San Jose, CA · On-site

Job Summary As a Design Verification intern, you will ensure the custom IPs powering our chips ... Familiarity with SystemVerilog, UVM, or Python * Familiarity with verification work and writing ...

Etched

DV Intern

San Jose, CA · On-site

Job Summary As aDesign Verification intern, you will ensure the custom IPs powering our chips ... UVM or formal verification experience * Ability to program with Python or another scripting ...

Etched

PD Intern

San Jose, CA · On-site

Job Summary As a Physical Design intern for Etched, you will be responsible for realizing our ... Familiarity with SystemVerilog, UVM, or Python * Familiarity with verification work and writing ...

Etched

PD Intern

San Jose, CA · On-site

Job Summary As a Physical Design intern for Etched, you will be responsible for realizing our ... Familiarity with SystemVerilog, UVM, or Python * Familiarity with verification work and writing ...

Advanced Micro Devices, Inc

$15.50 - $20/hr

As an AMD intern or co-op, you'll be placed at the epicenter of the AI ecosystem, working alongside ... Programming languages and scripts such as C++ /Python /C /Perl /Shell /UVM * Verilog and System ...

Advanced Micro Devices, Inc

$15.50 - $20/hr

As an AMD intern or co-op, you'll be placed at the epicenter of the AI ecosystem, working alongside ... Programming languages and scripts such as C++ /Python /C /Perl /Shell /UVM * Verilog and System ...

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Intern Uvm Verification information

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How much do intern uvm verification jobs pay per hour?

As of Sep 1, 2026, the average hourly pay for intern uvm verification in the United States is $19.38, according to ZipRecruiter salary data. Most workers in this role earn between $14.42 and $21.63 per hour, depending on experience, location, and employer.

What is the difference between Intern Uvm Verification vs Intern Digital Design?

AspectIntern Uvm VerificationIntern Digital Design
Required SkillsUVM, SystemVerilog, verification methodologiesDigital circuit design, VHDL/Verilog, simulation tools
Work EnvironmentVerification teams, simulation environmentsDesign teams, schematic capture, FPGA/ASIC design
Industry UsageSemiconductor, hardware verificationSemiconductor, hardware development

Intern Uvm Verification focuses on verifying hardware designs using UVM and SystemVerilog, while Intern Digital Design involves creating and simulating digital circuits. Both roles often share similar industry environments but differ in their core tasks and skill sets.

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Intern Uvm Verification jobs near you
Infographic showing various Intern Uvm Verification job openings in the United States as of August 2026, with employment types broken down into 1% As Needed, 80% Full Time, 15% Part Time, 3% Contract, and 1% Nights. Highlights an 90% Physical, 3% Hybrid, and 7% Remote job distribution, with an average salary of $40,304 per year, or $19.4 per hour.

Design Verification Engineer, Intern

Tenstorrent University Jobs

Boston, MA • On-site

Internship

Re-posted 24 days ago

Job description

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities.
At Tenstorrent, we believe the future of computing must be open, which is why our interns don't just watch from the sidelines - they help build the core of it. We provide a "code-to-career" pipeline where students collaborate with industry experts to solve high-stakes problems in RISC-V and AI hardware-software co-design. By joining us, you are taking an internship to democratize high-performance computers that are accessible to everyone.
As a Design Verification Engineer Intern on the SoC Digital Verification team, you will help ensure the functional correctness and robustness of Tenstorrent's next-generation RISC-V and AI accelerator SoCs. You will work on building and improving modern verification environments, developing tests and checkers, and analyzing coverage to sign off complex digital IP and subsystems. Your work directly contributes to the reliability of the chips that power our AI and high-performance computing roadmap.
We are looking for a minimum of 3 months for this role with the potential for extension to 6 months.
This role is hybrid, based in our Boston, MA office.
Who you are
  • Pursuing a B.S. , M.S. or PhD. in Electrical Engineering, Computer Engineering, Computer Science, or a related field with a focus on digital design and verification.
  • Strong understanding of digital logic design and computer architecture (pipelines, caches, interconnects, memory systems).
  • Familiar with HDLs such as Verilog/SystemVerilog, and interested in learning Formal verification, Cocotb, and UVM-based verification methodologies.
  • Comfortable working in Linux-based development environments and using scripting languages (e.g., Python, Shell, Perl) to automate tasks.
  • Detail-oriented problem solver who enjoys debugging complex issues, reasoning about corner cases, and working from specifications.
  • Collaborative team member with clear communication skills, able to document work and discuss trade-offs with RTL, architecture, and validation teams.

What We Need
  • Help develop and maintain SystemVerilog/UVM testbenches for SoC IP blocks and subsystems, including stimulus, checkers, and scoreboards.
  • Write and refine verification test plans from architectural and micro-architectural specifications, with a strong focus on corner cases and coverage.
  • Develop constrained-random and directed tests, run regressions, and triage failures by working closely with RTL designers to root-cause issues.
  • Analyze functional and code coverage results, identify gaps, and propose additional tests or checks to drive coverage closure.
  • Contribute to automation and infrastructure (scripts, Makefiles, CI hooks, dashboards) that improve verification productivity and debug turnaround time.
  • Partner with cross-functional teams (architecture, design, performance, validation) to align on expected behavior and sign-off criteria for silicon.
  • Have impact measured through coverage metrics achieved, quality and reproducibility of bugs found, and robustness of the verification environment you help build.

What You Will Learn
  • End-to-end SoC design and verification flow for cutting-edge RISC-V and AI accelerator architectures.
  • Industry-standard verification methodologies (SystemVerilog/UVM), including testbench architecture, stimulus generation, and scoreboard/checker design.
  • Hands-on experience with simulation, regression, and coverage tools used in large-scale industrial verification environments.
  • How to read and interpret hardware specifications, micro-architecture documents, and timing diagrams, and translate them into actionable tests and assertions.
  • Exposure to high-performance interconnects, memory controllers, and accelerators, and how they are verified at IP, subsystem, and SoC levels.
  • Best practices for collaborating in a silicon development team, including code review, documentation, and cross-site communication.

USA Hiring Timelines
This internship opportunity is available throughout our 3 terms with the following corresponding recruitment cycles:
  • Winter Term: Jan-Apr work term, Sept-Dec recruit.
  • Summer Term: May-Aug work term, Oct-Apr recruit.
  • Fall Term: Sept-Dec work term, Jan-Aug recruit.

Please note these timelines are for reference only. Actual timelines may vary.
This offer of employment is contingent upon the applicant being eligible to access U.S. export-controlled technology. Due to U.S. export laws, including those codified in the U.S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries (such as EAR Country Groups D:1, E1, and E2). These requirements apply to persons located in the U.S. and all countries outside the U.S. As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency. If employment is not possible due to U.S. export laws, any offer of employment will be rescinded.

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