Help develop and maintain SystemVerilog/UVM testbenches for SoC IP blocks and subsystems, including stimulus, checkers, and scoreboards. * Write and refine verification test plans from architectural ...
Help develop and maintain SystemVerilog/UVM testbenches for SoC IP blocks and subsystems, including stimulus, checkers, and scoreboards. * Write and refine verification test plans from architectural ...
Help develop and maintain SystemVerilog/UVM testbenches for SoC IP blocks and subsystems, including stimulus, checkers, and scoreboards. * Write and refine verification test plans from architectural ...
Help develop and maintain SystemVerilog/UVM testbenches for SoC IP blocks and subsystems, including stimulus, checkers, and scoreboards. * Write and refine verification test plans from architectural ...
... UVM) and verification monitors (SVA) UVM/SVA monitors, debugging failures, analyzing coverage information, and scripting Design Verification flows. The Design Engineering intern will work closely ...
... UVM) and verification monitors (SVA) UVM/SVA monitors, debugging failures, analyzing coverage information, and scripting Design Verification flows. The Design Engineering intern will work closely ...
SSG Design Engineering Intern (Fall 2026)
San Jose, CA · On-site
$35 - $62/hr
... UVM) and verification monitors (SVA) UVM/SVA monitors, debugging failures, analyzing coverage information, and scripting Design Verification flows. The Design Engineering intern will work closely ...
SSG Design Engineering Intern (Fall 2026)
San Jose, CA · On-site
$35 - $62/hr
... UVM) and verification monitors (SVA) UVM/SVA monitors, debugging failures, analyzing coverage information, and scripting Design Verification flows. The Design Engineering intern will work closely ...
... UVM) and verification monitors (SVA) UVM/SVA monitors, debugging failures, analyzing coverage information, and scripting Design Verification flows. The Design Engineering intern will work closely ...
... UVM) and verification monitors (SVA) UVM/SVA monitors, debugging failures, analyzing coverage information, and scripting Design Verification flows. The Design Engineering intern will work closely ...
... UVM) and verification monitors (SVA) UVM/SVA monitors, debugging failures, analyzing coverage information, and scripting Design Verification flows. The Design Engineering intern will work closely ...
... UVM) and verification monitors (SVA) UVM/SVA monitors, debugging failures, analyzing coverage information, and scripting Design Verification flows. The Design Engineering intern will work closely ...
DV Intern
San Jose, CA · On-site
Job Summary As a Design Verification intern, you will ensure the custom IPs powering our chips ... Familiarity with SystemVerilog, UVM, or Python * Familiarity with verification work and writing ...
Quick apply
DV Intern
San Jose, CA · On-site
Job Summary As a Design Verification intern, you will ensure the custom IPs powering our chips ... Familiarity with SystemVerilog, UVM, or Python * Familiarity with verification work and writing ...
DV Intern
San Jose, CA · On-site
Job Summary As aDesign Verification intern, you will ensure the custom IPs powering our chips ... UVM or formal verification experience * Ability to program with Python or another scripting ...
DV Intern
San Jose, CA · On-site
Job Summary As aDesign Verification intern, you will ensure the custom IPs powering our chips ... UVM or formal verification experience * Ability to program with Python or another scripting ...
PD Intern
San Jose, CA · On-site
Job Summary As a Physical Design intern for Etched, you will be responsible for realizing our ... Familiarity with SystemVerilog, UVM, or Python * Familiarity with verification work and writing ...
PD Intern
San Jose, CA · On-site
Job Summary As a Physical Design intern for Etched, you will be responsible for realizing our ... Familiarity with SystemVerilog, UVM, or Python * Familiarity with verification work and writing ...
PD Intern
San Jose, CA · On-site
Job Summary As a Physical Design intern for Etched, you will be responsible for realizing our ... Familiarity with SystemVerilog, UVM, or Python * Familiarity with verification work and writing ...
Quick apply
PD Intern
San Jose, CA · On-site
Job Summary As a Physical Design intern for Etched, you will be responsible for realizing our ... Familiarity with SystemVerilog, UVM, or Python * Familiarity with verification work and writing ...
FPGA Intern (Fall 2026) Internships at Astranis typically last for twelve weeks, and are hourly ... Experience with UVM and advanced SystemVerilog verification * Experience with Xilinx FPGAs
FPGA Intern (Fall 2026) Internships at Astranis typically last for twelve weeks, and are hourly ... Experience with UVM and advanced SystemVerilog verification * Experience with Xilinx FPGAs
$18 - $23.50/hr
The internship program requires some exposure to the programming and scripting languages like Verilog, System Verilog, UVM, C and C++, Perl, Python or assembly code. We expect that interns will be ...
$18 - $23.50/hr
The internship program requires some exposure to the programming and scripting languages like Verilog, System Verilog, UVM, C and C++, Perl, Python or assembly code. We expect that interns will be ...
Design Verification Intern
Burlingame, CA · On-site
$45 - $60/hr
Familiarity with verification methodologies for CPU or GPU designs. * Proficient in either ... UVM is a plus. * Prepared to collaborate with architects and designers to document test plans ...
Design Verification Intern
Burlingame, CA · On-site
$45 - $60/hr
Familiarity with verification methodologies for CPU or GPU designs. * Proficient in either ... UVM is a plus. * Prepared to collaborate with architects and designers to document test plans ...
Design Verification Intern
Burlingame, CA · On-site
$45 - $60/hr
Familiarity with verification methodologies for CPU or GPU designs. * Proficient in either ... UVM is a plus. * Prepared to collaborate with architects and designers to document test plans ...
Design Verification Intern
Burlingame, CA · On-site
$45 - $60/hr
Familiarity with verification methodologies for CPU or GPU designs. * Proficient in either ... UVM is a plus. * Prepared to collaborate with architects and designers to document test plans ...
Design Verification Intern
Burlingame, CA · On-site
$45 - $60/hr
Familiarity with verification methodologies for CPU or GPU designs. * Proficient in either ... UVM is a plus. * Prepared to collaborate with architects and designers to document test plans ...
Quick apply
Design Verification Intern
Burlingame, CA · On-site
$45 - $60/hr
Familiarity with verification methodologies for CPU or GPU designs. * Proficient in either ... UVM is a plus. * Prepared to collaborate with architects and designers to document test plans ...
RTL Intern
San Jose, CA · On-site
Job Summary As an RTL Intern at Etched, you will help design microarchitecture and implement logic ... Familiarity with SystemVerilog, UVM, or Python * Familiarity with verification work and writing ...
Quick apply
RTL Intern
San Jose, CA · On-site
Job Summary As an RTL Intern at Etched, you will help design microarchitecture and implement logic ... Familiarity with SystemVerilog, UVM, or Python * Familiarity with verification work and writing ...
RTL Intern
San Jose, CA · On-site
Job Summary As an RTL Intern at Etched, you will help design microarchitecture and implement logic ... Familiarity with SystemVerilog, UVM, or Python * Familiarity with verification work and writing ...
RTL Intern
San Jose, CA · On-site
Job Summary As an RTL Intern at Etched, you will help design microarchitecture and implement logic ... Familiarity with SystemVerilog, UVM, or Python * Familiarity with verification work and writing ...
FPGA Intern (Fall 2026)
San Francisco, CA · On-site
$29/hr
FPGA Intern (Fall 2026) Internships at Astranis typically last for twelve weeks, and are hourly ... Experience with UVM and advanced SystemVerilog verification * Experience with Xilinx FPGAs
FPGA Intern (Fall 2026)
San Francisco, CA · On-site
$29/hr
FPGA Intern (Fall 2026) Internships at Astranis typically last for twelve weeks, and are hourly ... Experience with UVM and advanced SystemVerilog verification * Experience with Xilinx FPGAs
Digital Logic + Design Verification Graduate Co-Op Program (US - Fall 2026)
Santa Clara, CA · On-site
$159K/yr
Exposure to UVM or formal verification methodologies * Experience with RTL design, simulation, or ... Additional compensation may be available for intern PhD candidates. We look forward to sharing more ...
Digital Logic + Design Verification Graduate Co-Op Program (US - Fall 2026)
Santa Clara, CA · On-site
$159K/yr
Exposure to UVM or formal verification methodologies * Experience with RTL design, simulation, or ... Additional compensation may be available for intern PhD candidates. We look forward to sharing more ...
Exposure to UVM or formal verification methodologies * Experience with RTL design, simulation, or ... Additional compensation may be available for intern PhD candidates. We look forward to sharing more ...
Exposure to UVM or formal verification methodologies * Experience with RTL design, simulation, or ... Additional compensation may be available for intern PhD candidates. We look forward to sharing more ...
Intern Uvm Verification information
See salary details
$9.13 - $11.65
9% of jobs
$11.65 - $14.16
8% of jobs
$14.81 is the 25th percentile. Wages below this are outliers.
$14.16 - $16.67
28% of jobs
The median wage is $17.34 / hr.
$16.67 - $19.19
16% of jobs
$20.91 is the 75th percentile. Wages above this are outliers.
$19.19 - $21.70
20% of jobs
$21.70 - $24.21
9% of jobs
$24.21 - $26.73
4% of jobs
$26.73 - $29.24
1% of jobs
$29.24 - $31.75
1% of jobs
$31.75 - $34.27
1% of jobs
$34.27 - $36.78
2% of jobs
$9
$19
$36
How much do intern uvm verification jobs pay per hour?
As of Jul 22, 2026, the average hourly pay for intern uvm verification in the United States is $19.38, according to ZipRecruiter salary data. Most workers in this role earn between $14.42 and $21.63 per hour, depending on experience, location, and employer.
What is the difference between Intern Uvm Verification vs Intern Digital Design?
| Aspect | Intern Uvm Verification | Intern Digital Design |
|---|---|---|
| Required Skills | UVM, SystemVerilog, verification methodologies | Digital circuit design, VHDL/Verilog, simulation tools |
| Work Environment | Verification teams, simulation environments | Design teams, schematic capture, FPGA/ASIC design |
| Industry Usage | Semiconductor, hardware verification | Semiconductor, hardware development |
Intern Uvm Verification focuses on verifying hardware designs using UVM and SystemVerilog, while Intern Digital Design involves creating and simulating digital circuits. Both roles often share similar industry environments but differ in their core tasks and skill sets.
More about Intern Uvm Verification jobs
What cities are hiring for Intern Uvm Verification jobs? Cities with the most Intern Uvm Verification job openings:
What are the most commonly searched types of Uvm Verification jobs? The most popular types of Uvm Verification jobs are:
What states have the most Intern Uvm Verification jobs? States with the most job openings for Intern Uvm Verification jobs include:
What job categories do people searching Intern Uvm Verification jobs look for? The top searched job categories for Intern Uvm Verification jobs are:
Internship
Re-posted 13 days ago
Job description
Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities.
At Tenstorrent, we believe the future of computing must be open, which is why our interns don't just watch from the sidelines - they help build the core of it. We provide a "code-to-career" pipeline where students collaborate with industry experts to solve high-stakes problems in RISC-V and AI hardware-software co-design. By joining us, you are taking an internship to democratize high-performance computers that are accessible to everyone.
As a Design Verification Engineer Intern on the SoC Digital Verification team, you will help ensure the functional correctness and robustness of Tenstorrent's next-generation RISC-V and AI accelerator SoCs. You will work on building and improving modern verification environments, developing tests and checkers, and analyzing coverage to sign off complex digital IP and subsystems. Your work directly contributes to the reliability of the chips that power our AI and high-performance computing roadmap.
We are looking for a minimum of 3 months for this role with the potential for extension to 6 months.
This role is hybrid, based in our Boston, MA office.
Who you are
What We Need
What You Will Learn
USA Hiring Timelines
This internship opportunity is available throughout our 3 terms with the following corresponding recruitment cycles:
Please note these timelines are for reference only. Actual timelines may vary.
This offer of employment is contingent upon the applicant being eligible to access U.S. export-controlled technology. Due to U.S. export laws, including those codified in the U.S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries (such as EAR Country Groups D:1, E1, and E2). These requirements apply to persons located in the U.S. and all countries outside the U.S. As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency. If employment is not possible due to U.S. export laws, any offer of employment will be rescinded.
At Tenstorrent, we believe the future of computing must be open, which is why our interns don't just watch from the sidelines - they help build the core of it. We provide a "code-to-career" pipeline where students collaborate with industry experts to solve high-stakes problems in RISC-V and AI hardware-software co-design. By joining us, you are taking an internship to democratize high-performance computers that are accessible to everyone.
As a Design Verification Engineer Intern on the SoC Digital Verification team, you will help ensure the functional correctness and robustness of Tenstorrent's next-generation RISC-V and AI accelerator SoCs. You will work on building and improving modern verification environments, developing tests and checkers, and analyzing coverage to sign off complex digital IP and subsystems. Your work directly contributes to the reliability of the chips that power our AI and high-performance computing roadmap.
We are looking for a minimum of 3 months for this role with the potential for extension to 6 months.
This role is hybrid, based in our Boston, MA office.
Who you are
- Pursuing a B.S. , M.S. or PhD. in Electrical Engineering, Computer Engineering, Computer Science, or a related field with a focus on digital design and verification.
- Strong understanding of digital logic design and computer architecture (pipelines, caches, interconnects, memory systems).
- Familiar with HDLs such as Verilog/SystemVerilog, and interested in learning Formal verification, Cocotb, and UVM-based verification methodologies.
- Comfortable working in Linux-based development environments and using scripting languages (e.g., Python, Shell, Perl) to automate tasks.
- Detail-oriented problem solver who enjoys debugging complex issues, reasoning about corner cases, and working from specifications.
- Collaborative team member with clear communication skills, able to document work and discuss trade-offs with RTL, architecture, and validation teams.
What We Need
- Help develop and maintain SystemVerilog/UVM testbenches for SoC IP blocks and subsystems, including stimulus, checkers, and scoreboards.
- Write and refine verification test plans from architectural and micro-architectural specifications, with a strong focus on corner cases and coverage.
- Develop constrained-random and directed tests, run regressions, and triage failures by working closely with RTL designers to root-cause issues.
- Analyze functional and code coverage results, identify gaps, and propose additional tests or checks to drive coverage closure.
- Contribute to automation and infrastructure (scripts, Makefiles, CI hooks, dashboards) that improve verification productivity and debug turnaround time.
- Partner with cross-functional teams (architecture, design, performance, validation) to align on expected behavior and sign-off criteria for silicon.
- Have impact measured through coverage metrics achieved, quality and reproducibility of bugs found, and robustness of the verification environment you help build.
What You Will Learn
- End-to-end SoC design and verification flow for cutting-edge RISC-V and AI accelerator architectures.
- Industry-standard verification methodologies (SystemVerilog/UVM), including testbench architecture, stimulus generation, and scoreboard/checker design.
- Hands-on experience with simulation, regression, and coverage tools used in large-scale industrial verification environments.
- How to read and interpret hardware specifications, micro-architecture documents, and timing diagrams, and translate them into actionable tests and assertions.
- Exposure to high-performance interconnects, memory controllers, and accelerators, and how they are verified at IP, subsystem, and SoC levels.
- Best practices for collaborating in a silicon development team, including code review, documentation, and cross-site communication.
USA Hiring Timelines
This internship opportunity is available throughout our 3 terms with the following corresponding recruitment cycles:
- Winter Term: Jan-Apr work term, Sept-Dec recruit.
- Summer Term: May-Aug work term, Oct-Apr recruit.
- Fall Term: Sept-Dec work term, Jan-Aug recruit.
Please note these timelines are for reference only. Actual timelines may vary.
This offer of employment is contingent upon the applicant being eligible to access U.S. export-controlled technology. Due to U.S. export laws, including those codified in the U.S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries (such as EAR Country Groups D:1, E1, and E2). These requirements apply to persons located in the U.S. and all countries outside the U.S. As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency. If employment is not possible due to U.S. export laws, any offer of employment will be rescinded.