Application Engineer Intern Requisition No.: 7800-1031 Type of Position: Regular, Exempt Reports to ... Familiarity with Hardware Description Languages (HDL) such as Verilog, System Verilog or VHDL
Application Engineer Intern Requisition No.: 7800-1031 Type of Position: Regular, Exempt Reports to ... Familiarity with Hardware Description Languages (HDL) such as Verilog, System Verilog or VHDL
US 2026 Hardware - Digital Intern
San Jose, CA ยท On-site
$35 - $45/hr
About the Role We are seeking a Digital Hardware Intern to support the design, verification, and ... Responsibilities Support RTL design using Verilog or SystemVerilog Assist in writing testbenches ...
US 2026 Hardware - Digital Intern
San Jose, CA ยท On-site
$35 - $45/hr
About the Role We are seeking a Digital Hardware Intern to support the design, verification, and ... Responsibilities Support RTL design using Verilog or SystemVerilog Assist in writing testbenches ...
US 2026 Hardware - Digital Intern
San Jose, CA ยท On-site
$35 - $45/hr
About the Role We are seeking a Digital Hardware Intern to support the design, verification, and ... Responsibilities โข Support RTL design using Verilog or SystemVerilog โข Assist in writing ...
US 2026 Hardware - Digital Intern
San Jose, CA ยท On-site
$35 - $45/hr
About the Role We are seeking a Digital Hardware Intern to support the design, verification, and ... Responsibilities โข Support RTL design using Verilog or SystemVerilog โข Assist in writing ...
Intern, Engineering
Marlborough, MA ยท On-site
$17.25 - $22.50/hr
The FPGA Developer Intern is responsible for working as a team member to support the development of ... Experience with Verilog and FPGA * Experience with Electrical CAD/Schematic software * Experience ...
Intern, Engineering
Marlborough, MA ยท On-site
$17.25 - $22.50/hr
The FPGA Developer Intern is responsible for working as a team member to support the development of ... Experience with Verilog and FPGA * Experience with Electrical CAD/Schematic software * Experience ...
FPGA Intern (Fall 2026) Internships at Astranis typically last for twelve weeks, and are hourly ... Proficiency with Verilog/SystemVerilog for synthesis * Don't meet them all? Not a problem. Please ...
FPGA Intern (Fall 2026) Internships at Astranis typically last for twelve weeks, and are hourly ... Proficiency with Verilog/SystemVerilog for synthesis * Don't meet them all? Not a problem. Please ...
Intern This opportunity resides with Warfare Systems (WS) , a business group within HII's Mission ... Introduction to hardware description languages (Verilog/VHDL basics) Week 3: Hardware Tools * FPGA ...
Intern This opportunity resides with Warfare Systems (WS) , a business group within HII's Mission ... Introduction to hardware description languages (Verilog/VHDL basics) Week 3: Hardware Tools * FPGA ...
Intern This opportunity resides with Warfare Systems (WS), a business group within HII's Mission ... Verilog/VHDL basics) Week 3: Hardware Tools FPGA development environment setup (Quartus/Vivado ...
Intern This opportunity resides with Warfare Systems (WS), a business group within HII's Mission ... Verilog/VHDL basics) Week 3: Hardware Tools FPGA development environment setup (Quartus/Vivado ...
Intern This opportunity resides with Warfare Systems (WS), a business group within HII's Mission ... Verilog/VHDL basics) Week 3: Hardware Tools FPGA development environment setup (Quartus/Vivado ...
Intern This opportunity resides with Warfare Systems (WS), a business group within HII's Mission ... Verilog/VHDL basics) Week 3: Hardware Tools FPGA development environment setup (Quartus/Vivado ...
Electrical Engineering Intern (Fall 2026)
Redmond, WA ยท On-site
$70K/yr
Write and debug embedded C code or HDL (e.g., Verilog/VHDL) What You Will Need: * Current ... As an engineering intern, you are expected to embody them in every design decision, debugging ...
Electrical Engineering Intern (Fall 2026)
Redmond, WA ยท On-site
$70K/yr
Write and debug embedded C code or HDL (e.g., Verilog/VHDL) What You Will Need: * Current ... As an engineering intern, you are expected to embody them in every design decision, debugging ...
RTL Intern
San Jose, CA ยท On-site
Job Summary As an RTL Intern at Etched, you will help design microarchitecture and implement logic in verilog. You will work with cutting-edge machine learning architectures, contribute to RTL block ...
RTL Intern
San Jose, CA ยท On-site
Job Summary As an RTL Intern at Etched, you will help design microarchitecture and implement logic in verilog. You will work with cutting-edge machine learning architectures, contribute to RTL block ...
Electrical Engineering Intern (Fall 2026)
El Segundo, CA ยท On-site
$70K/yr
Write and debug embedded C code or HDL (e.g., Verilog/VHDL) What You Will Need: * Current ... As an engineering intern, you are expected to embody them in every design decision, debugging ...
Electrical Engineering Intern (Fall 2026)
El Segundo, CA ยท On-site
$70K/yr
Write and debug embedded C code or HDL (e.g., Verilog/VHDL) What You Will Need: * Current ... As an engineering intern, you are expected to embody them in every design decision, debugging ...
Electrical Engineering Intern (Fall 2026)
Redmond, WA ยท On-site
$70K/yr
Write and debug embedded C code or HDL (e.g., Verilog/VHDL) What You Will Need: * Current ... As an engineering intern, you are expected to embody them in every design decision, debugging ...
Electrical Engineering Intern (Fall 2026)
Redmond, WA ยท On-site
$70K/yr
Write and debug embedded C code or HDL (e.g., Verilog/VHDL) What You Will Need: * Current ... As an engineering intern, you are expected to embody them in every design decision, debugging ...
Write and debug embedded C code or HDL (e.g., Verilog/VHDL) What You Will Need: * Current ... As an engineering intern, you are expected to embody them in every design decision, debugging ...
Quick apply
Write and debug embedded C code or HDL (e.g., Verilog/VHDL) What You Will Need: * Current ... As an engineering intern, you are expected to embody them in every design decision, debugging ...
RTL Intern
San Jose, CA ยท On-site
Job Summary As an RTL Intern at Etched, you will help design microarchitecture and implement logic in verilog. You will work with cutting-edge machine learning architectures, contribute to RTL block ...
Quick apply
RTL Intern
San Jose, CA ยท On-site
Job Summary As an RTL Intern at Etched, you will help design microarchitecture and implement logic in verilog. You will work with cutting-edge machine learning architectures, contribute to RTL block ...
Write and debug embedded C code or HDL (e.g., Verilog/VHDL) What You Will Need: * Current ... As an engineering intern, you are expected to embody them in every design decision, debugging ...
Quick apply
Write and debug embedded C code or HDL (e.g., Verilog/VHDL) What You Will Need: * Current ... As an engineering intern, you are expected to embody them in every design decision, debugging ...
Electrical Engineering Intern (Fall 2026)
El Segundo, CA ยท On-site
$70K/yr
Write and debug embedded C code or HDL (e.g., Verilog/VHDL) What You Will Need: * Current ... As an engineering intern, you are expected to embody them in every design decision, debugging ...
Electrical Engineering Intern (Fall 2026)
El Segundo, CA ยท On-site
$70K/yr
Write and debug embedded C code or HDL (e.g., Verilog/VHDL) What You Will Need: * Current ... As an engineering intern, you are expected to embody them in every design decision, debugging ...
FPGA Intern (Fall 2026)
San Francisco, CA ยท On-site
$29/hr
FPGA Intern (Fall 2026) Internships at Astranis typically last for twelve weeks, and are hourly ... Proficiency with Verilog/SystemVerilog for synthesis * Don't meet them all? Not a problem. Please ...
FPGA Intern (Fall 2026)
San Francisco, CA ยท On-site
$29/hr
FPGA Intern (Fall 2026) Internships at Astranis typically last for twelve weeks, and are hourly ... Proficiency with Verilog/SystemVerilog for synthesis * Don't meet them all? Not a problem. Please ...
DFT Intern
San Jose, CA ยท On-site
$17.50 - $23.50/hr
Job Summary As a DFT Intern at Etched, you will help review and refine DFT flow automation to ... Familiarity with a hardware description language (Verilog or SystemVerilog) * Exposure to ASIC or ...
DFT Intern
San Jose, CA ยท On-site
$17.50 - $23.50/hr
Job Summary As a DFT Intern at Etched, you will help review and refine DFT flow automation to ... Familiarity with a hardware description language (Verilog or SystemVerilog) * Exposure to ASIC or ...
DFT Intern
San Jose, CA ยท On-site
$17.50 - $23.50/hr
Job Summary As a DFT Intern at Etched, you will help review and refine DFT flow automation to ... Familiarity with a hardware description language (Verilog or SystemVerilog) * Exposure to ASIC or ...
Quick apply
DFT Intern
San Jose, CA ยท On-site
$17.50 - $23.50/hr
Job Summary As a DFT Intern at Etched, you will help review and refine DFT flow automation to ... Familiarity with a hardware description language (Verilog or SystemVerilog) * Exposure to ASIC or ...
$18 - $23.50/hr
The internship program requires some exposure to the programming and scripting languages like Verilog, System Verilog, UVM, C and C++, Perl, Python or assembly code. We expect that interns will be ...
$18 - $23.50/hr
The internship program requires some exposure to the programming and scripting languages like Verilog, System Verilog, UVM, C and C++, Perl, Python or assembly code. We expect that interns will be ...
Verilog Intern information
See salary details
$8.89 - $10.29
3% of jobs
$10.29 - $11.69
3% of jobs
$11.69 - $13.09
3% of jobs
$13.09 - $14.49
9% of jobs
$14.94 is the 25th percentile. Wages below this are outliers.
$14.49 - $15.89
21% of jobs
The median wage is $16.47 / hr.
$15.89 - $17.29
26% of jobs
$18.39 is the 75th percentile. Wages above this are outliers.
$17.29 - $18.68
13% of jobs
$18.68 - $20.08
12% of jobs
$20.08 - $21.48
4% of jobs
$21.48 - $22.88
3% of jobs
$22.88 - $24.28
3% of jobs
$8
$17
$24
How much do verilog intern jobs pay per hour?
What are the key skills and qualifications needed to thrive in the Verilog Intern position, and why are they important?
To thrive as a Verilog Intern, you need a solid understanding of digital logic design, foundational knowledge of hardware description languages (HDLs) like Verilog, and typically a background in electrical or computer engineering. Familiarity with simulation tools such as ModelSim or Vivado, and basic experience in using version control systems like Git, are commonly expected. Strong problem-solving abilities, attention to detail, and collaborative communication set exceptional candidates apart. These skills are crucial for effectively contributing to design, simulation, and verification tasks in a team-oriented engineering environment.
What is a Verilog Intern job?
A Verilog Intern is typically a student or entry-level engineer who assists in designing, coding, and testing digital circuits using Verilog, a hardware description language (HDL). Their responsibilities may include writing testbenches, simulating circuits, and debugging design issues under the guidance of senior engineers. This role provides hands-on experience in FPGA or ASIC design and helps build a foundation in digital logic design, synthesis, and verification.
What types of projects or tasks can I expect to work on as a Verilog Intern?
As a Verilog Intern, you can expect to assist in the design, simulation, and verification of digital circuits using Verilog HDL. Your daily tasks might include writing and debugging Verilog code, running testbenches, analyzing simulation results, and collaborating with senior engineers to meet project requirements. You'll likely work as part of a team, participating in code reviews and learning industry best practices regarding hardware design and version control. This hands-on experience allows you to build technical proficiency while gaining insight into the hardware development lifecycle, setting a foundation for future roles in digital design.

(7800-1031) Application Engineer Intern
Santa Clara, CA โข On-site
Internship
Posted 13 days ago
Job description
Position Profile Name:Application Engineer Intern
Requisition No.:7800-1031
Type of Position:Regular, Exempt
Reports to:Applications Manager
Department:
Marketing
Location:
Santa Clara, CA
Contact:hr@achronix.com
Job Description/Responsibilities
- Provide support to customers worldwide, to resolve challenging technical issues and ensure successful integration of Achronix programmable logic solutions
- Work with senior Applications team members to create reference/demo designs and other technical collateral such as user guides and application notes to showcase and document Achronix FPGA features to customers
- Work closely with Achronix Engineering teams to drive product planning and implementation efforts
- Some travel may be required
- Familiarity with Hardware Description Languages (HDL) such as Verilog, System Verilog or VHDL
- Strong digital logic design background
- Understanding of FPGA/programmable logic architecture and design flows is a plus
- Good communication and writing skills with ability to multi-task
- Relevant university coursework
- Bachelors or Master's degree in Electrical Engineering, Computer Science/Computer Engineering
- Digital Integrated Circuit Design or similar
- VLSI Systems Design or similar
- Computer Architecture and Design or similar
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About Achronix Semiconductor
Sourced by ZipRecruiter
Industry
Semiconductor and electronic component manufacturing
Company size
51 - 200 Employees
Headquarters location
Santa Clara, CA, US
Year founded
2004