RTL Intern
San Jose, CA · On-site
Job Summary As an RTL Intern at Etched, you will help design microarchitecture and implement logic in verilog. You will work with cutting-edge machine learning architectures, contribute to RTL block ...
RTL Intern
San Jose, CA · On-site
Job Summary As an RTL Intern at Etched, you will help design microarchitecture and implement logic in verilog. You will work with cutting-edge machine learning architectures, contribute to RTL block ...
RTL Intern
San Jose, CA · On-site
Job Summary As an RTL Intern at Etched, you will help design microarchitecture and implement logic in verilog. You will work with cutting-edge machine learning architectures, contribute to RTL block ...
Quick apply
RTL Intern
San Jose, CA · On-site
Job Summary As an RTL Intern at Etched, you will help design microarchitecture and implement logic in verilog. You will work with cutting-edge machine learning architectures, contribute to RTL block ...
FPGA Intern (Fall 2026)
San Francisco, CA · On-site
$29/hr
FPGA Intern (Fall 2026) Internships at Astranis typically last for twelve weeks, and are hourly ... Proficiency with Verilog/SystemVerilog for synthesis * Don't meet them all? Not a problem. Please ...
FPGA Intern (Fall 2026)
San Francisco, CA · On-site
$29/hr
FPGA Intern (Fall 2026) Internships at Astranis typically last for twelve weeks, and are hourly ... Proficiency with Verilog/SystemVerilog for synthesis * Don't meet them all? Not a problem. Please ...
Engineering Intern (Fall 2026)
Syracuse, NY · On-site
$16.50 - $21.50/hr
As an engineering intern, you will contribute to the design, development, implementation and ... Design, develop, implement, test and optimize firmware using VHDL/Verilog * Work with FPGAs and ...
Engineering Intern (Fall 2026)
Syracuse, NY · On-site
$16.50 - $21.50/hr
As an engineering intern, you will contribute to the design, development, implementation and ... Design, develop, implement, test and optimize firmware using VHDL/Verilog * Work with FPGAs and ...
Engineering Intern (Fall 2026)
$16.50 - $21.50/hr
As an engineering intern, you will contribute to the design, development, implementation and ... Design, develop, implement, test and optimize firmware using VHDL/Verilog * Work with FPGAs and ...
Engineering Intern (Fall 2026)
$16.50 - $21.50/hr
As an engineering intern, you will contribute to the design, development, implementation and ... Design, develop, implement, test and optimize firmware using VHDL/Verilog * Work with FPGAs and ...
Engineering Intern (Fall 2026)
Syracuse, NY · On-site
$16.50 - $21.50/hr
As an engineering intern, you will contribute to the design, development, implementation and ... Design, develop, implement, test and optimize firmware using VHDL/Verilog * Work with FPGAs and ...
Engineering Intern (Fall 2026)
Syracuse, NY · On-site
$16.50 - $21.50/hr
As an engineering intern, you will contribute to the design, development, implementation and ... Design, develop, implement, test and optimize firmware using VHDL/Verilog * Work with FPGAs and ...
Engineering Intern (Fall 2026)
$16.50 - $21.50/hr
As an engineering intern, you will contribute to the design, development, implementation and ... Design, develop, implement, test and optimize firmware using VHDL/Verilog * Work with FPGAs and ...
Quick apply
Engineering Intern (Fall 2026)
$16.50 - $21.50/hr
As an engineering intern, you will contribute to the design, development, implementation and ... Design, develop, implement, test and optimize firmware using VHDL/Verilog * Work with FPGAs and ...
DFT Intern
San Jose, CA · On-site
Job Summary As a DFT Intern at Etched, you will help review and refine DFT flow automation to ... Familiarity with a hardware description language (Verilog or SystemVerilog) * Exposure to ASIC or ...
DFT Intern
San Jose, CA · On-site
Job Summary As a DFT Intern at Etched, you will help review and refine DFT flow automation to ... Familiarity with a hardware description language (Verilog or SystemVerilog) * Exposure to ASIC or ...
DFT Intern
San Jose, CA · On-site
Job Summary As a DFT Intern at Etched, you will help review and refine DFT flow automation to ... Familiarity with a hardware description language (Verilog or SystemVerilog) * Exposure to ASIC or ...
Quick apply
DFT Intern
San Jose, CA · On-site
Job Summary As a DFT Intern at Etched, you will help review and refine DFT flow automation to ... Familiarity with a hardware description language (Verilog or SystemVerilog) * Exposure to ASIC or ...
$18 - $23.50/hr
The internship program requires some exposure to the programming and scripting languages like Verilog, System Verilog, UVM, C and C++, Perl, Python or assembly code. We expect that interns will be ...
$18 - $23.50/hr
The internship program requires some exposure to the programming and scripting languages like Verilog, System Verilog, UVM, C and C++, Perl, Python or assembly code. We expect that interns will be ...
Logic design, implementation, and verification using Verilog, System Verilog, and any required programing and scripting languages. * Synthesize and optimize RTL for timing, area and power.
Logic design, implementation, and verification using Verilog, System Verilog, and any required programing and scripting languages. * Synthesize and optimize RTL for timing, area and power.
... Verilog (SV) models. You will also work with chip and DV leads to plan, setup, & execute AMS/UVM ... As an intern, you'll collaborate with experienced engineers to solve real-world challenges ...
... Verilog (SV) models. You will also work with chip and DV leads to plan, setup, & execute AMS/UVM ... As an intern, you'll collaborate with experienced engineers to solve real-world challenges ...
... a summer-long non-technical intern project, in addition to engineering assignment. • ... VHDL, Verilog, System Verilog, Cadence, HFSS, MATLAB or LabVIEW is a plus. Pay Information ...
... a summer-long non-technical intern project, in addition to engineering assignment. • ... VHDL, Verilog, System Verilog, Cadence, HFSS, MATLAB or LabVIEW is a plus. Pay Information ...
We're now looking for a Formal Verification Intern.NVIDIA is seeking elite Formal Verification ... Practical experience with Verilog or SystemVerilog, including temporal logic assertions.
We're now looking for a Formal Verification Intern.NVIDIA is seeking elite Formal Verification ... Practical experience with Verilog or SystemVerilog, including temporal logic assertions.
As a ML Software Engineer Intern in AI/CAD Integration, you will collaborate with our team of ... Knowledge of chip design file formats (GDSII, LEF/DEF, Verilog, SPICE) * Experience with shell ...
As a ML Software Engineer Intern in AI/CAD Integration, you will collaborate with our team of ... Knowledge of chip design file formats (GDSII, LEF/DEF, Verilog, SPICE) * Experience with shell ...
As a ML Software Engineer Intern in AI/CAD Integration, you will collaborate with our team of ... Knowledge of chip design file formats (GDSII, LEF/DEF, Verilog, SPICE) * Experience with shell ...
As a ML Software Engineer Intern in AI/CAD Integration, you will collaborate with our team of ... Knowledge of chip design file formats (GDSII, LEF/DEF, Verilog, SPICE) * Experience with shell ...
As a ML Software Engineer Intern in AI/CAD Integration, you will collaborate with our team of ... Knowledge of chip design file formats (GDSII, LEF/DEF, Verilog, SPICE) * Experience with shell ...
Quick apply
As a ML Software Engineer Intern in AI/CAD Integration, you will collaborate with our team of ... Knowledge of chip design file formats (GDSII, LEF/DEF, Verilog, SPICE) * Experience with shell ...
Job Summary The Analog Design Intern will assist engineers in designing and developing Technology ... Build Verilog/Verilog-a models for analog circuit blocks to enable efficient simulations at chip ...
Job Summary The Analog Design Intern will assist engineers in designing and developing Technology ... Build Verilog/Verilog-a models for analog circuit blocks to enable efficient simulations at chip ...
We're now looking for a Formal Verification Intern.NVIDIA is seeking elite Formal Verification ... Practical experience with Verilog or SystemVerilog, including temporal logic assertions.
We're now looking for a Formal Verification Intern.NVIDIA is seeking elite Formal Verification ... Practical experience with Verilog or SystemVerilog, including temporal logic assertions.
Job Summary The Analog Design Intern will assist engineers in designing and developing Technology ... Build Verilog/Verilog-a models for analog circuit blocks to enable efficient simulations at chip ...
Job Summary The Analog Design Intern will assist engineers in designing and developing Technology ... Build Verilog/Verilog-a models for analog circuit blocks to enable efficient simulations at chip ...
Verilog Intern information
See salary details
$8.89 - $10.29
3% of jobs
$10.29 - $11.69
3% of jobs
$11.69 - $13.09
3% of jobs
$13.09 - $14.49
9% of jobs
$14.94 is the 25th percentile. Wages below this are outliers.
$14.49 - $15.89
21% of jobs
The median wage is $16.47 / hr.
$15.89 - $17.29
26% of jobs
$18.39 is the 75th percentile. Wages above this are outliers.
$17.29 - $18.68
13% of jobs
$18.68 - $20.08
12% of jobs
$20.08 - $21.48
4% of jobs
$21.48 - $22.88
3% of jobs
$22.88 - $24.28
3% of jobs
$8
$17
$24
How much do verilog intern jobs pay per hour?
As of Jun 9, 2026, the average hourly pay for verilog intern in the United States is $17.04, according to ZipRecruiter salary data. Most workers in this role earn between $14.42 and $19.23 per hour, depending on experience, location, and employer.
What are the key skills and qualifications needed to thrive in the Verilog Intern position, and why are they important?
To thrive as a Verilog Intern, you need a solid understanding of digital logic design, foundational knowledge of hardware description languages (HDLs) like Verilog, and typically a background in electrical or computer engineering. Familiarity with simulation tools such as ModelSim or Vivado, and basic experience in using version control systems like Git, are commonly expected. Strong problem-solving abilities, attention to detail, and collaborative communication set exceptional candidates apart. These skills are crucial for effectively contributing to design, simulation, and verification tasks in a team-oriented engineering environment.
What is a Verilog Intern job?
A Verilog Intern is typically a student or entry-level engineer who assists in designing, coding, and testing digital circuits using Verilog, a hardware description language (HDL). Their responsibilities may include writing testbenches, simulating circuits, and debugging design issues under the guidance of senior engineers. This role provides hands-on experience in FPGA or ASIC design and helps build a foundation in digital logic design, synthesis, and verification.
What types of projects or tasks can I expect to work on as a Verilog Intern?
As a Verilog Intern, you can expect to assist in the design, simulation, and verification of digital circuits using Verilog HDL. Your daily tasks might include writing and debugging Verilog code, running testbenches, analyzing simulation results, and collaborating with senior engineers to meet project requirements. You'll likely work as part of a team, participating in code reviews and learning industry best practices regarding hardware design and version control. This hands-on experience allows you to build technical proficiency while gaining insight into the hardware development lifecycle, setting a foundation for future roles in digital design.
More about Verilog Intern jobs
What cities are hiring for Verilog Intern jobs? Cities with the most Verilog Intern job openings:
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What states have the most Verilog Intern jobs? States with the most job openings for Verilog Intern jobs include:
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Internship
Posted 2 days ago
Job description
About Etched
Etched is building the world's first AI inference system purpose-built for transformers - delivering over 10x higher performance and dramatically lower cost and latency than a B200. With Etched ASICs, you can build products that would be impossible with GPUs, like real-time video generation models and extremely deep & parallel chain-of-thought reasoning agents. Backed by hundreds of millions from top-tier investors and staffed by leading engineers, Etched is redefining the infrastructure layer for the fastest growing industry in history.
Job Summary
As an RTL Intern at Etched, you will help design microarchitecture and implement logic in verilog. You will work with cutting-edge machine learning architectures, contribute to RTL block development, and participate in the full design cycle-from microarchitecture discussions to synthesis and timing feedback. You do not necessarily need prior ML/AI hardware experience; just the ability to learn quickly in a fast-paced, high-autonomy environment. We are looking for Fall '26, Spring '27, and Summer '27 interns.
You may be a good fit if you have
Strong candidates may also have experience with
We encourage you to apply even if you do not believe you meet every single qualification.
Program details
For any questions, contact internships@etched.com
How we're different
Etched believes in the Bitter Lesson. We think most of the progress in the AI field has come from using more FLOPs to train and run models, and the best way to get more FLOPs is to build model-specific hardware. Larger and larger training runs encourage companies to consolidate around fewer model architectures, which creates a market for single-model ASICs.
We are a fully in-person team in San Jose (Santana Row), and greatly value engineering skills. We do not have boundaries between engineering and research, and we expect all of our technical staff to contribute to both as needed.
Etched is building the world's first AI inference system purpose-built for transformers - delivering over 10x higher performance and dramatically lower cost and latency than a B200. With Etched ASICs, you can build products that would be impossible with GPUs, like real-time video generation models and extremely deep & parallel chain-of-thought reasoning agents. Backed by hundreds of millions from top-tier investors and staffed by leading engineers, Etched is redefining the infrastructure layer for the fastest growing industry in history.
Job Summary
As an RTL Intern at Etched, you will help design microarchitecture and implement logic in verilog. You will work with cutting-edge machine learning architectures, contribute to RTL block development, and participate in the full design cycle-from microarchitecture discussions to synthesis and timing feedback. You do not necessarily need prior ML/AI hardware experience; just the ability to learn quickly in a fast-paced, high-autonomy environment. We are looking for Fall '26, Spring '27, and Summer '27 interns.
You may be a good fit if you have
- Progress towards a Bachelor's, Master's, or PhD degree in electrical engineering, computer engineering, or a related field.
- Familiarity with high-speed digital logic
- Exposure to ASIC or SoC design concepts
- Familiarity with SystemVerilog, UVM, or Python
- Familiarity with verification work and writing test benches
- Familiarity with physical design flows and tooling
- Are able to learn quickly about transformers and other aspects of modern artificial intelligence
Strong candidates may also have experience with
- Familiarity with transformer models and machine learning
- Familiarity with numerical representations and functions
- Familiarity with clocking and reset schemes
- Ability to program with Python or another scripting language
We encourage you to apply even if you do not believe you meet every single qualification.
Program details
- 12-week paid internship
- Generous housing support for those relocating
- Daily lunch and dinner in our office
- Based at our office in San Jose, CA
- Direct mentorship from industry leaders and world-class engineers
- Opportunity to work on one of the most important problems of our time
For any questions, contact internships@etched.com
How we're different
Etched believes in the Bitter Lesson. We think most of the progress in the AI field has come from using more FLOPs to train and run models, and the best way to get more FLOPs is to build model-specific hardware. Larger and larger training runs encourage companies to consolidate around fewer model architectures, which creates a market for single-model ASICs.
We are a fully in-person team in San Jose (Santana Row), and greatly value engineering skills. We do not have boundaries between engineering and research, and we expect all of our technical staff to contribute to both as needed.