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Verilog Intern Jobs (NOW HIRING)

Etched

DFT Intern

San Jose, CA · On-site

$17.50 - $23.50/hr

Job Summary As a DFT Intern at Etched, you will help review and refine DFT flow automation to ... Familiarity with a hardware description language (Verilog or SystemVerilog) * Exposure to ASIC or ...

Ambarella

$18 - $23.50/hr

The internship program requires some exposure to the programming and scripting languages like Verilog, System Verilog, UVM, C and C++, Perl, Python or assembly code. We expect that interns will be ...

Ambarella

Logic design, implementation, and verification using Verilog, System Verilog, and any required programing and scripting languages. * Synthesize and optimize RTL for timing, area and power.

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How much do verilog intern jobs pay per hour?

As of Aug 14, 2026, the average hourly pay for verilog intern in the United States is $17.04, according to ZipRecruiter salary data. Most workers in this role earn between $14.42 and $19.23 per hour, depending on experience, location, and employer.

What are the key skills and qualifications needed to thrive as a Verilog intern?

To thrive as a Verilog Intern, you need a solid understanding of digital logic design, foundational knowledge of hardware description languages (HDLs) like Verilog, and typically a background in electrical or computer engineering. Familiarity with simulation tools such as ModelSim or Vivado, and basic experience in using version control systems like Git, are commonly expected. Strong problem-solving abilities, attention to detail, and collaborative communication set exceptional candidates apart. These skills are crucial for effectively contributing to design, simulation, and verification tasks in a team-oriented engineering environment.

What is a Verilog intern?

A Verilog Intern is typically a student or entry-level engineer who assists in designing, coding, and testing digital circuits using Verilog, a hardware description language (HDL). Their responsibilities may include writing testbenches, simulating circuits, and debugging design issues under the guidance of senior engineers. This role provides hands-on experience in FPGA or ASIC design and helps build a foundation in digital logic design, synthesis, and verification.

What types of projects or tasks can I expect to work on as a Verilog intern?

As a Verilog Intern, you can expect to assist in the design, simulation, and verification of digital circuits using Verilog HDL. Your daily tasks might include writing and debugging Verilog code, running testbenches, analyzing simulation results, and collaborating with senior engineers to meet project requirements. You'll likely work as part of a team, participating in code reviews and learning industry best practices regarding hardware design and version control. This hands-on experience allows you to build technical proficiency while gaining insight into the hardware development lifecycle, setting a foundation for future roles in digital design.

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Verilog Intern jobs near you
Infographic showing various Verilog Intern job openings in the United States as of August 2026, with employment types broken down into 38% Internship, 49% Full Time, and 13% Part Time. Highlights an 100% In-person job distribution, with an average salary of $35,436 per year, or $17 per hour.

DFT Intern

Etched

San Jose, CA • On-site

$17.50 - $23.50/hr

Internship

Re-posted 2 days ago

Job description

About Etched
Etched is building hardware for frontier intelligence. We co-design chips, racks, software, and manufacturing to deliver best-in-class throughput and latency across both prefill and decode workloads. Our first products are heavily focused on inference. Backed by hundreds of millions from top-tier investors and staffed by leading engineers, Etched is redefining the infrastructure layer for the fastest growing industry in history.
Job Summary
As a DFT Intern at Etched, you will help review and refine DFT flow automation to support chip-level regression on Caelius. You will work across frontend and backend design teams, contribute to DFT verification (including MBIST, Scan, BSCAN, and SSN simulations), and develop flows for various ATPG fault models. You do not necessarily need prior DFT experience; just the ability to learn quickly in a fast-paced, high-autonomy environment. We are looking for Summer '26, Fall '26, Spring '27, and Summer '27 interns.
You may be a good fit if you have
  • Progress towards a Bachelor's, Master's, or PhD degree in electrical engineering, computer engineering, or a related field.
  • Familiarity with a hardware description language (Verilog or SystemVerilog)
  • Exposure to ASIC or SoC design concepts
  • Familiarity with digital logic design fundamentals
  • Familiarity with standard ASIC design flow steps (synthesis, STA, DFT)
  • Familiarity with scripting in Python, Tcl, or another language
  • Are able to learn quickly about transformers and other aspects of modern artificial intelligence

Strong candidates may also have experience with
  • Knowledge of DFT concepts such as MBIST, scan insertion, and scan compression
  • Experience with Tessent or similar DFT tooling
  • Familiarity with ATPG fault models (SAF, TDF, BDF, IDDQ, PDF)
  • Exposure to DFT flow automation or regression infrastructure
  • Familiarity with clocking and reset schemes

We encourage you to apply even if you do not believe you meet every single qualification.
Program details
  • 12-week paid internship
  • Generous housing support for those relocating
  • Daily lunch and dinner in our office
  • Based at our office in San Jose, CA
  • Direct mentorship from industry leaders and world-class engineers
  • Opportunity to work on one of the most important problems of our time

For any questions, contact internships@etched.com.
How we're different
Etched believes in the Bitter Lesson. We are the first inference-focused frontier AI system. Our addressable market is the entirety of inference, unlike many of our competitors.
We are a fully in-person team in San Jose (Santana Row), and greatly value engineering skills. We do not have boundaries between engineering and research, and we expect all of our technical staff to contribute to both and work across disciplines as needed.

Apply