As an intern, you are paired with full-time employees who act as mentors, collaborating with you on ... The hardware team at Jane Street works on both FPGA and ASIC designs. Depending on your background ...
As an intern, you are paired with full-time employees who act as mentors, collaborating with you on ... The hardware team at Jane Street works on both FPGA and ASIC designs. Depending on your background ...
As an intern, you are paired with full-time employees who act as mentors, collaborating with you on ... The hardware team at Jane Street works on both FPGA and ASIC designs. Depending on your background ...
As an intern, you are paired with full-time employees who act as mentors, collaborating with you on ... The hardware team at Jane Street works on both FPGA and ASIC designs. Depending on your background ...
Physical Design Intern
$35 - $45/hr
As a Physical Design Intern, you will collaborate with experienced engineers to transform RTL ... Execute ASIC physical design implementation flows, including floorplanning, placement, clock tree ...
Physical Design Intern
$35 - $45/hr
As a Physical Design Intern, you will collaborate with experienced engineers to transform RTL ... Execute ASIC physical design implementation flows, including floorplanning, placement, clock tree ...
Physical Design Intern
San Jose, CA · On-site
$35 - $45/hr
As a Physical Design Intern, you will collaborate with experienced engineers to transform RTL ... Execute ASIC physical design implementation flows, including floorplanning, placement, clock tree ...
Physical Design Intern
San Jose, CA · On-site
$35 - $45/hr
As a Physical Design Intern, you will collaborate with experienced engineers to transform RTL ... Execute ASIC physical design implementation flows, including floorplanning, placement, clock tree ...
Physical Design Intern
San Jose, CA · On-site
$35 - $45/hr
As a Physical Design Intern, you will collaborate with experienced engineers to transform RTL ... Execute ASIC physical design implementation flows, including floorplanning, placement, clock tree ...
Quick apply
Physical Design Intern
San Jose, CA · On-site
$35 - $45/hr
As a Physical Design Intern, you will collaborate with experienced engineers to transform RTL ... Execute ASIC physical design implementation flows, including floorplanning, placement, clock tree ...
DFT Intern
San Jose, CA · On-site
$17.50 - $23.50/hr
Job Summary As a DFT Intern at Etched, you will help review and refine DFT flow automation to ... Exposure to ASIC or SoC design concepts * Familiarity with digital logic design fundamentals
DFT Intern
San Jose, CA · On-site
$17.50 - $23.50/hr
Job Summary As a DFT Intern at Etched, you will help review and refine DFT flow automation to ... Exposure to ASIC or SoC design concepts * Familiarity with digital logic design fundamentals
DFT Intern
San Jose, CA · On-site
$17.50 - $23.50/hr
Job Summary As a DFT Intern at Etched, you will help review and refine DFT flow automation to ... Exposure to ASIC or SoC design concepts * Familiarity with digital logic design fundamentals
Quick apply
DFT Intern
San Jose, CA · On-site
$17.50 - $23.50/hr
Job Summary As a DFT Intern at Etched, you will help review and refine DFT flow automation to ... Exposure to ASIC or SoC design concepts * Familiarity with digital logic design fundamentals
SI/PI Intern
San Jose, CA · On-site
Job Summary As a Signal Integrity / Power Integrity Intern, you will help design and validate the ... You will work closely with package, PCB, ASIC, and system engineers to analyze high-speed ...
Quick apply
SI/PI Intern
San Jose, CA · On-site
Job Summary As a Signal Integrity / Power Integrity Intern, you will help design and validate the ... You will work closely with package, PCB, ASIC, and system engineers to analyze high-speed ...
SI/PI Intern
San Jose, CA · On-site
Job Summary As a Signal Integrity / Power Integrity Intern, you will help design and validate the ... You will work closely with package, PCB, ASIC, and system engineers to analyze high-speed ...
SI/PI Intern
San Jose, CA · On-site
Job Summary As a Signal Integrity / Power Integrity Intern, you will help design and validate the ... You will work closely with package, PCB, ASIC, and system engineers to analyze high-speed ...
As an intern in the Physical Design (PD) team, you will work on high-performance designs going into ... ASIC. This role is on-site, 40 hours, based out of Santa Clara, CA or Austin, TX. Who You Are
As an intern in the Physical Design (PD) team, you will work on high-performance designs going into ... ASIC. This role is on-site, 40 hours, based out of Santa Clara, CA or Austin, TX. Who You Are
Machine Learning for Physical Design Intern - CPU/AI Hardware
Santa Clara, CA · Hybrid
$50 - $70/hr
As an intern in the Physical Design (PD) team, you will work on high-performance designs going into ... ASIC. This role is on-site, hybrid, based out of Santa Clara, CA working 4 days in office, 1 day ...
Machine Learning for Physical Design Intern - CPU/AI Hardware
Santa Clara, CA · Hybrid
$50 - $70/hr
As an intern in the Physical Design (PD) team, you will work on high-performance designs going into ... ASIC. This role is on-site, hybrid, based out of Santa Clara, CA working 4 days in office, 1 day ...
PD Intern
San Jose, CA · On-site
Job Summary As a Physical Design intern for Etched, you will be responsible for realizing our ... Exposure to ASIC or SoC design concepts * Familiarity with SystemVerilog, UVM, or Python
PD Intern
San Jose, CA · On-site
Job Summary As a Physical Design intern for Etched, you will be responsible for realizing our ... Exposure to ASIC or SoC design concepts * Familiarity with SystemVerilog, UVM, or Python
DV Intern
San Jose, CA · On-site
Job Summary As a Design Verification intern, you will ensure the custom IPs powering our chips ... Exposure to ASIC or SoC design concepts * Familiarity with SystemVerilog, UVM, or Python
Quick apply
DV Intern
San Jose, CA · On-site
Job Summary As a Design Verification intern, you will ensure the custom IPs powering our chips ... Exposure to ASIC or SoC design concepts * Familiarity with SystemVerilog, UVM, or Python
RTL Intern
San Jose, CA · On-site
Job Summary As an RTL Intern at Etched, you will help design microarchitecture and implement logic ... Exposure to ASIC or SoC design concepts * Familiarity with SystemVerilog, UVM, or Python
RTL Intern
San Jose, CA · On-site
Job Summary As an RTL Intern at Etched, you will help design microarchitecture and implement logic ... Exposure to ASIC or SoC design concepts * Familiarity with SystemVerilog, UVM, or Python
PD Intern
San Jose, CA · On-site
Job Summary As a Physical Design intern for Etched, you will be responsible for realizing our ... Exposure to ASIC or SoC design concepts * Familiarity with SystemVerilog, UVM, or Python
Quick apply
PD Intern
San Jose, CA · On-site
Job Summary As a Physical Design intern for Etched, you will be responsible for realizing our ... Exposure to ASIC or SoC design concepts * Familiarity with SystemVerilog, UVM, or Python
DV Intern
San Jose, CA · On-site
Job Summary As aDesign Verification intern, you will ensure the custom IPs powering our chips ... Exposure to ASIC or SoC design concepts * Familiarity with SystemVerilog, UVM, or Python
DV Intern
San Jose, CA · On-site
Job Summary As aDesign Verification intern, you will ensure the custom IPs powering our chips ... Exposure to ASIC or SoC design concepts * Familiarity with SystemVerilog, UVM, or Python
US 2026 Hardware - Digital Intern
San Jose, CA · On-site
$35 - $45/hr
About the Role We are seeking a Digital Hardware Intern to support the design, verification, and ... SoC or ASIC development flow is a plus • Team-oriented with strong communication and ...
US 2026 Hardware - Digital Intern
San Jose, CA · On-site
$35 - $45/hr
About the Role We are seeking a Digital Hardware Intern to support the design, verification, and ... SoC or ASIC development flow is a plus • Team-oriented with strong communication and ...
RTL Intern
San Jose, CA · On-site
Job Summary As an RTL Intern at Etched, you will help design microarchitecture and implement logic ... Exposure to ASIC or SoC design concepts * Familiarity with SystemVerilog, UVM, or Python
Quick apply
RTL Intern
San Jose, CA · On-site
Job Summary As an RTL Intern at Etched, you will help design microarchitecture and implement logic ... Exposure to ASIC or SoC design concepts * Familiarity with SystemVerilog, UVM, or Python
US 2026 Hardware - Digital Intern
$35 - $45/hr
... ASIC development flow is a plus Team-oriented with strong communication and documentation skills Salary Range: $35-45 USD/hr TetraMem celebrates diversity and is committed to creating an inclusive ...
US 2026 Hardware - Digital Intern
$35 - $45/hr
... ASIC development flow is a plus Team-oriented with strong communication and documentation skills Salary Range: $35-45 USD/hr TetraMem celebrates diversity and is committed to creating an inclusive ...
AI Vision Processors For Edge Applications Our solutions make cameras smarter by extracting valuable data from high-resolution video streams. Position Responsibilities: * Designing and implementing ...
AI Vision Processors For Edge Applications Our solutions make cameras smarter by extracting valuable data from high-resolution video streams. Position Responsibilities: * Designing and implementing ...
Asic Intern information
See salary details
$9.13 - $11.65
9% of jobs
$11.65 - $14.16
8% of jobs
$14.81 is the 25th percentile. Wages below this are outliers.
$14.16 - $16.67
28% of jobs
The median wage is $17.34 / hr.
$16.67 - $19.19
16% of jobs
$20.91 is the 75th percentile. Wages above this are outliers.
$19.19 - $21.70
20% of jobs
$21.70 - $24.21
9% of jobs
$24.21 - $26.73
4% of jobs
$26.73 - $29.24
1% of jobs
$29.24 - $31.75
1% of jobs
$31.75 - $34.27
1% of jobs
$34.27 - $36.78
2% of jobs
$9
$19
$36
How much do asic intern jobs pay per hour?
What are the key skills and qualifications needed to thrive in the Asic Intern position, and why are they important?
To thrive as an ASIC Intern, you need a solid understanding of digital design fundamentals, hardware description languages (such as Verilog or VHDL), and coursework or experience in electrical or computer engineering. Familiarity with tools like simulation software (ModelSim, Synopsys VCS), FPGA prototyping platforms, and version control systems (Git) is typically required. Attention to detail, problem-solving skills, and the ability to collaborate effectively with engineering teams will help you stand out. These competencies are crucial because ASIC design is a complex, team-oriented process that relies on both technical acumen and strong interpersonal skills to ensure successful chip development.
What are the big 4 internships?
What is an ASIC Intern job?
An ASIC Intern assists in the design, verification, and testing of Application-Specific Integrated Circuits (ASICs). They work with design engineers to create and simulate circuit layouts, debug hardware, and optimize performance. Responsibilities may include using hardware description languages (HDLs) like Verilog or VHDL, writing test scripts, and analyzing power and timing constraints. This role provides hands-on experience in chip development, allowing interns to apply theoretical knowledge to real-world semiconductor projects.
What is an ASIC intern?
Is $23 an hour good for an internship?
What kind of projects and daily tasks can I expect as an ASIC Intern?
As an ASIC Intern, you can expect to contribute to various stages of the chip development process, including RTL design, verification, simulation, and debugging. Your daily tasks may involve writing and testing code, running simulations, documenting results, and collaborating with senior engineers to resolve technical challenges. It's common to participate in team meetings to discuss project progress and receive feedback on your work, providing valuable exposure to industry best practices. This hands-on experience not only develops your technical skills but also helps you understand the workflow and expectations in a professional ASIC design environment.
Are ASIC jobs in demand?

Job description
Our goal is to give you a real sense of what it's like to work at Jane Street full time while also providing a truly unparalleled educational experience. As an intern, you are paired with full-time employees who act as mentors, collaborating with you on real-world projects we actually need done.
In this internship, you'll learn how we use tools to make programming faster, more pleasant, and more reliable. We apply these same principles to our hardware engineering work, and we're looking for people who are interested in using programming language technology to improve the process of designing, testing, and validating hardware designs. We use Hardcaml, an OCaml library for succinctly describing hardware in RTL. Hardcaml is tightly integrated into our development environment, so you'll also gain lots of exposure to the libraries and tools that are foundational to our internal systems. No previous knowledge of Hardcaml is required.
The hardware team at Jane Street works on both FPGA and ASIC designs. Depending on your background and experience, we'll craft a project that gives you exposure to our shared Hardcaml tech stack, as well as targeting an FPGA or ASIC platform.
During the program, you'll dive deep on one project, mentored closely by the full-time employees who helped design it. Some intern projects consider big-picture questions that we're still trying to figure out, while others involve building something new. Your mentors will help you gain a better understanding of the wide range of problems we solve every day. We expect interns to build hardware applications from concept to a working design; your projects will predominantly involve OCaml & Hardcaml, for both RTL design and testing/integration.
If you'd like to learn more, you can read about our interview process, meet some of our newest hires, or check out our OCaml All The Way Down talk and Programmable Hardware podcast episode. You can also learn more about Jane Street's internship program here.
About You
We don't expect you to have a background in finance, OCaml, functional programming, or any other specific field- we're looking for smart people who enjoy solving interesting problems. We're more interested in how you think and learn than what you currently know. You should be:
- Comfortable with a software programming language
- Experienced with a Hardware Description (or Construction) language (VHDL, Verilog, Chisel, Pymtl, or other), for both writing and testing hardware designs
- Experienced working with FPGA or ASIC vendor tools - Vivado or Quartus for FPGAs, Genus or Innovus for ASICs
- Experienced with building a working hardware project (either FPGA or ASIC) through an academic, professional, or personal project
- Interested in learning how to use FPGAs or ASICs in the context of networking
If you're a recruiting agency and want to partner with us, please reach out to agency-partnerships@janestreet.com.
About Jane Street
Sourced by ZipRecruiter
Industry
Finance and insurance
Company size
1,001 - 5,000 Employees
Headquarters location
New York, NY, US
Year founded
2000