ASIC Design Intern
Beaverton, OR · On-site
We are seeking a motivated ASIC Design Intern (Co-op or Internship) to join our engineering team during the summer term. This role is designed for students who are eager to gain hands-on experience ...
Beaverton, OR · On-site
We are seeking a motivated ASIC Design Intern (Co-op or Internship) to join our engineering team during the summer term. This role is designed for students who are eager to gain hands-on experience ...
Beaverton, OR · On-site
We are seeking a motivated ASIC Design Intern (Co-op or Internship) to join our engineering team during the summer term. This role is designed for students who are eager to gain hands-on experience ...
$35 - $45/hr
About the Role We are seeking a driven Embedded Software Intern to join our engineering team and ... Support integration and performance tuning on FPGA and ASIC platforms. * Assist in implementing and ...
$35 - $45/hr
About the Role We are seeking a driven Embedded Software Intern to join our engineering team and ... Support integration and performance tuning on FPGA and ASIC platforms. * Assist in implementing and ...
San Jose, CA · On-site
$35 - $45/hr
About the Role We are seeking a driven Embedded Software Intern to join our engineering team and ... Support integration and performance tuning on FPGA and ASIC platforms. * Assist in implementing and ...
San Jose, CA · On-site
$35 - $45/hr
About the Role We are seeking a driven Embedded Software Intern to join our engineering team and ... Support integration and performance tuning on FPGA and ASIC platforms. * Assist in implementing and ...
San Jose, CA · On-site
$35 - $45/hr
Willingness to learn ASIC design flows, tools, and methodologies. * Strong attention to detail and ability to follow structured workflows. Preferred Qualifications * Introductory exposure to DFT ...
San Jose, CA · On-site
$35 - $45/hr
Willingness to learn ASIC design flows, tools, and methodologies. * Strong attention to detail and ability to follow structured workflows. Preferred Qualifications * Introductory exposure to DFT ...
San Jose, CA · On-site
$35 - $45/hr
Willingness to learn ASIC design flows, tools, and methodologies. * Strong attention to detail and ability to follow structured workflows. Preferred Qualifications * Introductory exposure to DFT ...
San Jose, CA · On-site
$35 - $45/hr
Willingness to learn ASIC design flows, tools, and methodologies. * Strong attention to detail and ability to follow structured workflows. Preferred Qualifications * Introductory exposure to DFT ...
$35 - $45/hr
Willingness to learn ASIC design flows, tools, and methodologies. * Strong attention to detail and ability to follow structured workflows. Preferred Qualifications * Introductory exposure to DFT ...
Quick apply
$35 - $45/hr
Willingness to learn ASIC design flows, tools, and methodologies. * Strong attention to detail and ability to follow structured workflows. Preferred Qualifications * Introductory exposure to DFT ...
$35 - $45/hr
... ASIC development flow is a plus Team-oriented with strong communication and documentation skills Salary Range: $35-45 USD/hr
$35 - $45/hr
... ASIC development flow is a plus Team-oriented with strong communication and documentation skills Salary Range: $35-45 USD/hr
San Jose, CA · On-site
$35 - $45/hr
About the Role We are seeking a Digital Hardware Intern to support the design, verification, and ... SoC or ASIC development flow is a plus • Team-oriented with strong communication and ...
San Jose, CA · On-site
$35 - $45/hr
About the Role We are seeking a Digital Hardware Intern to support the design, verification, and ... SoC or ASIC development flow is a plus • Team-oriented with strong communication and ...
San Jose, CA · On-site
Job Summary As a DFT Intern at Etched, you will help review and refine DFT flow automation to ... Exposure to ASIC or SoC design concepts * Familiarity with digital logic design fundamentals
San Jose, CA · On-site
Job Summary As a DFT Intern at Etched, you will help review and refine DFT flow automation to ... Exposure to ASIC or SoC design concepts * Familiarity with digital logic design fundamentals
San Jose, CA · On-site
Job Summary As a DFT Intern at Etched, you will help review and refine DFT flow automation to ... Exposure to ASIC or SoC design concepts * Familiarity with digital logic design fundamentals
Quick apply
San Jose, CA · On-site
Job Summary As a DFT Intern at Etched, you will help review and refine DFT flow automation to ... Exposure to ASIC or SoC design concepts * Familiarity with digital logic design fundamentals
The intern can face some unique challenges including both ASIC and MEMs design or quality issues. This will require a strong knowledge in data analysis, setting up design of experiments and the use ...
The intern can face some unique challenges including both ASIC and MEMs design or quality issues. This will require a strong knowledge in data analysis, setting up design of experiments and the use ...
The intern can face some unique challenges including both ASIC and MEMs design or quality issues. This will require a strong knowledge in data analysis, setting up design of experiments and the use ...
The intern can face some unique challenges including both ASIC and MEMs design or quality issues. This will require a strong knowledge in data analysis, setting up design of experiments and the use ...
The intern can face some unique challenges including both ASIC and MEMs design or quality issues. This will require a strong knowledge in data analysis, setting up design of experiments and the use ...
The intern can face some unique challenges including both ASIC and MEMs design or quality issues. This will require a strong knowledge in data analysis, setting up design of experiments and the use ...
Austin, TX · On-site
$50 - $70/hr
As an intern in the Physical Design (PD) team, you will work on high-performance designs going into ... ASIC. This role is on-site, 40 hours, based out of Santa Clara, CA or Austin, TX. Who You Are
Austin, TX · On-site
$50 - $70/hr
As an intern in the Physical Design (PD) team, you will work on high-performance designs going into ... ASIC. This role is on-site, 40 hours, based out of Santa Clara, CA or Austin, TX. Who You Are
Santa Clara, CA · Hybrid
$50 - $70/hr
As an intern in the Physical Design (PD) team, you will work on high-performance designs going into ... ASIC. This role is on-site, hybrid, based out of Santa Clara, CA working 4 days in office, 1 day ...
Santa Clara, CA · Hybrid
$50 - $70/hr
As an intern in the Physical Design (PD) team, you will work on high-performance designs going into ... ASIC. This role is on-site, hybrid, based out of Santa Clara, CA working 4 days in office, 1 day ...
$35 - $45/hr
About the Company: At SK Hynix Memory Solution, we're at the forefront of semiconductor innovation, developing advanced memory solutions that power everything from smartphones to data centers. As a ...
New
Quick apply
$35 - $45/hr
About the Company: At SK Hynix Memory Solution, we're at the forefront of semiconductor innovation, developing advanced memory solutions that power everything from smartphones to data centers. As a ...
New
Participate in the ASIC/SoC design flow , including RTL development, verification, and system ... Student / Intern (Fixed Term) Shift: Shift 1 (United States of America) Primary Location: San Jose ...
New
Participate in the ASIC/SoC design flow , including RTL development, verification, and system ... Student / Intern (Fixed Term) Shift: Shift 1 (United States of America) Primary Location: San Jose ...
New
San Jose, CA · On-site
$35 - $45/hr
About the Company: At SK Hynix Memory Solution, we're at the forefront of semiconductor innovation, developing advanced memory solutions that power everything from smartphones to data centers. As a ...
New
San Jose, CA · On-site
$35 - $45/hr
About the Company: At SK Hynix Memory Solution, we're at the forefront of semiconductor innovation, developing advanced memory solutions that power everything from smartphones to data centers. As a ...
New
San Jose, CA · On-site
$35 - $45/hr
About the Company: At SK Hynix Memory Solution, we're at the forefront of semiconductor innovation, developing advanced memory solutions that power everything from smartphones to data centers. As a ...
San Jose, CA · On-site
$35 - $45/hr
About the Company: At SK Hynix Memory Solution, we're at the forefront of semiconductor innovation, developing advanced memory solutions that power everything from smartphones to data centers. As a ...
San Jose, CA · On-site
Job Summary As aDesign Verification intern, you will ensure the custom IPs powering our chips ... Exposure to ASIC or SoC design concepts * Familiarity with SystemVerilog, UVM, or Python
San Jose, CA · On-site
Job Summary As aDesign Verification intern, you will ensure the custom IPs powering our chips ... Exposure to ASIC or SoC design concepts * Familiarity with SystemVerilog, UVM, or Python
$9.13 - $11.65
9% of jobs
$11.65 - $14.16
8% of jobs
$14.81 is the 25th percentile. Wages below this are outliers.
$14.16 - $16.67
28% of jobs
The median wage is $17.34 / hr.
$16.67 - $19.19
16% of jobs
$20.91 is the 75th percentile. Wages above this are outliers.
$19.19 - $21.70
20% of jobs
$21.70 - $24.21
9% of jobs
$24.21 - $26.73
4% of jobs
$26.73 - $29.24
1% of jobs
$29.24 - $31.75
1% of jobs
$31.75 - $34.27
1% of jobs
$34.27 - $36.78
2% of jobs
$9
$19
$36
To thrive as an ASIC Intern, you need a solid understanding of digital design fundamentals, hardware description languages (such as Verilog or VHDL), and coursework or experience in electrical or computer engineering. Familiarity with tools like simulation software (ModelSim, Synopsys VCS), FPGA prototyping platforms, and version control systems (Git) is typically required. Attention to detail, problem-solving skills, and the ability to collaborate effectively with engineering teams will help you stand out. These competencies are crucial because ASIC design is a complex, team-oriented process that relies on both technical acumen and strong interpersonal skills to ensure successful chip development.
An ASIC Intern assists in the design, verification, and testing of Application-Specific Integrated Circuits (ASICs). They work with design engineers to create and simulate circuit layouts, debug hardware, and optimize performance. Responsibilities may include using hardware description languages (HDLs) like Verilog or VHDL, writing test scripts, and analyzing power and timing constraints. This role provides hands-on experience in chip development, allowing interns to apply theoretical knowledge to real-world semiconductor projects.
As an ASIC Intern, you can expect to contribute to various stages of the chip development process, including RTL design, verification, simulation, and debugging. Your daily tasks may involve writing and testing code, running simulations, documenting results, and collaborating with senior engineers to resolve technical challenges. It's common to participate in team meetings to discuss project progress and receive feedback on your work, providing valuable exposure to industry best practices. This hands-on experience not only develops your technical skills but also helps you understand the workflow and expectations in a professional ASIC design environment.

Full-time
Posted 5 days ago