As an intern in the Physical Design (PD) team, you will work on high-performance designs going into ... ASIC. This role is on-site, 40 hours, based out of Santa Clara, CA or Austin, TX. Who You Are
As an intern in the Physical Design (PD) team, you will work on high-performance designs going into ... ASIC. This role is on-site, 40 hours, based out of Santa Clara, CA or Austin, TX. Who You Are
Machine Learning for Physical Design Intern - CPU/AI Hardware
Austin, TX · On-site
$50 - $70/hr
As an intern in the Physical Design (PD) team, you will work on high-performance designs going into ... ASIC. This role is on-site, 40 hours, based out of Santa Clara, CA or Austin, TX. Who You Are
Machine Learning for Physical Design Intern - CPU/AI Hardware
Austin, TX · On-site
$50 - $70/hr
As an intern in the Physical Design (PD) team, you will work on high-performance designs going into ... ASIC. This role is on-site, 40 hours, based out of Santa Clara, CA or Austin, TX. Who You Are
Asic Intern information
See Texas salary details
$8.51 - $10.85
9% of jobs
$10.85 - $13.19
8% of jobs
$13.80 is the 25th percentile. Wages below this are outliers.
$13.19 - $15.53
28% of jobs
The median wage is $16.16 / hr.
$15.53 - $17.88
16% of jobs
$19.48 is the 75th percentile. Wages above this are outliers.
$17.88 - $20.22
20% of jobs
$20.22 - $22.56
9% of jobs
$22.56 - $24.90
4% of jobs
$24.90 - $27.24
1% of jobs
$27.24 - $29.58
1% of jobs
$29.58 - $31.92
1% of jobs
$31.92 - $34.26
2% of jobs
$8
$18
$34
How much do asic intern jobs pay per hour?
What are the key skills and qualifications needed to thrive in the ASIC intern position, and why are they important?
To thrive as an ASIC Intern, you need a solid understanding of digital design fundamentals, hardware description languages (such as Verilog or VHDL), and coursework or experience in electrical or computer engineering. Familiarity with tools like simulation software (ModelSim, Synopsys VCS), FPGA prototyping platforms, and version control systems (Git) is typically required. Attention to detail, problem-solving skills, and the ability to collaborate effectively with engineering teams will help you stand out. These competencies are crucial because ASIC design is a complex, team-oriented process that relies on both technical acumen and strong interpersonal skills to ensure successful chip development.
What is an ASIC intern?
An ASIC Intern assists in the design, verification, and testing of Application-Specific Integrated Circuits (ASICs). They work with design engineers to create and simulate circuit layouts, debug hardware, and optimize performance. Responsibilities may include using hardware description languages (HDLs) like Verilog or VHDL, writing test scripts, and analyzing power and timing constraints. This role provides hands-on experience in chip development, allowing interns to apply theoretical knowledge to real-world semiconductor projects.
What kind of projects and daily tasks can I expect as an ASIC intern?
As an ASIC Intern, you can expect to contribute to various stages of the chip development process, including RTL design, verification, simulation, and debugging. Your daily tasks may involve writing and testing code, running simulations, documenting results, and collaborating with senior engineers to resolve technical challenges. It's common to participate in team meetings to discuss project progress and receive feedback on your work, providing valuable exposure to industry best practices. This hands-on experience not only develops your technical skills but also helps you understand the workflow and expectations in a professional ASIC design environment.

$50 - $70/hr
Other
Re-posted 27 days ago
Job description
As an intern in the Physical Design (PD) team, you will work on high-performance designs going into industry leading AI/ML architectures. The student coming into this role will develop ML-based tools and flows to improve the PPA (Performance Power Area) and turnaround time for all aspects of chip implementation from synthesis to tapeout for various IPs. The work is done collaboratively with a group of highly experienced engineers across various domains of the ASIC.
This role is on-site, 40 hours, based out of Santa Clara, CA or Austin, TX.
Who You Are
- Currently pursuing a BS/MS/PhD in EE/ECE/CE/CS.
- Possessing deep knowledge of math, probability, statistics, and algorithms.
- Experienced in solving problems with Machine Learning models.
- Skilled in algorithms, data structures, and software development using Python and C/C++.
What We Need
- Ability to develop ML-based tools to improve PPA and turnaround time for chip implementation.
- Work closely with other PD engineers to develop ML tools for areas such as synthesis, PnR, timing closure, and power grid analysis.
- Responsibility for selecting appropriate datasets, data representation methods, and implementing new algorithms.
- Capability to run machine learning tests, perform statistical analysis, and fine-tune models using test results.
What You Will Learn
- How to apply ML systems and flows to high-performance designs for industry-leading AI/ML architectures.
- Practical experience in extending existing ML systems and implementing cutting-edge algorithms.
- Gain exposure to core physical design fundamentals, including synthesis, place and route, and timing analysis.
- Experience collaborating with a group of highly experienced engineers across various domains of the ASIC implementation.
Compensation for all interns at Tenstorrent ranges from $50/hr - $70/hr including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.
Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.