As an intern in the Physical Design (PD) team, you will work on high-performance designs going into ... ASIC. This role is on-site, 40 hours, based out of Santa Clara, CA or Austin, TX. Who You Are
As an intern in the Physical Design (PD) team, you will work on high-performance designs going into ... ASIC. This role is on-site, 40 hours, based out of Santa Clara, CA or Austin, TX. Who You Are
Machine Learning for Physical Design Intern - CPU/AI Hardware
Austin, TX · On-site
$50 - $70/hr
As an intern in the Physical Design (PD) team, you will work on high-performance designs going into ... ASIC. This role is on-site, 40 hours, based out of Santa Clara, CA or Austin, TX. Who You Are
Machine Learning for Physical Design Intern - CPU/AI Hardware
Austin, TX · On-site
$50 - $70/hr
As an intern in the Physical Design (PD) team, you will work on high-performance designs going into ... ASIC. This role is on-site, 40 hours, based out of Santa Clara, CA or Austin, TX. Who You Are
Asic Design Intern information
See Texas salary details
$8.51 - $10.85
9% of jobs
$10.85 - $13.19
8% of jobs
$13.80 is the 25th percentile. Wages below this are outliers.
$13.19 - $15.53
28% of jobs
The median wage is $16.16 / hr.
$15.53 - $17.88
16% of jobs
$19.48 is the 75th percentile. Wages above this are outliers.
$17.88 - $20.22
20% of jobs
$20.22 - $22.56
9% of jobs
$22.56 - $24.90
4% of jobs
$24.90 - $27.24
1% of jobs
$27.24 - $29.58
1% of jobs
$29.58 - $31.92
1% of jobs
$31.92 - $34.26
2% of jobs
$8
$18
$34
How much do asic design intern jobs pay per hour?
What is an ASIC Design Intern?
An ASIC Design Intern assists in the design, verification, and testing of Application-Specific Integrated Circuits (ASICs). Interns work with experienced engineers to develop digital or analog circuit designs, run simulations, and debug hardware issues. They gain hands-on experience with design tools, scripting languages, and verification methodologies. This role provides valuable industry exposure and helps interns build skills in VLSI, RTL design, and semiconductor development.
What are the key skills and qualifications needed to thrive in the ASIC Design Intern position, and why are they important?
To thrive as an ASIC Design Intern, you need a solid foundation in digital logic design, computer architecture, and proficiency with hardware description languages such as Verilog or VHDL, typically supported by coursework in electrical or computer engineering. Familiarity with industry-standard EDA tools like Cadence or Synopsys and experience with simulation and debugging environments are highly valued. Strong problem-solving skills, attention to detail, and effective communication make you stand out in collaborative team projects. These skills ensure you can contribute effectively to complex design tasks, learn quickly, and integrate seamlessly into professional ASIC development teams.
What are the typical responsibilities of an ASIC Design Intern during their internship?
As an ASIC Design Intern, your responsibilities may include assisting with the design and verification of digital circuits, creating testbenches, running simulations, and helping debug hardware issues alongside experienced engineers. You may also document design processes, participate in reviews, and contribute to tool flow development or optimization tasks. Interns often work closely with senior design, verification, and physical design engineers, gaining exposure to a variety of stages in the ASIC development lifecycle. This hands-on experience not only builds your technical expertise but also helps you develop teamwork and project management skills, which are essential for advancing in hardware engineering roles.
$50 - $70/hr
Internship
Re-posted 3 days ago
Job description
As an intern in the Physical Design (PD) team, you will work on high-performance designs going into industry leading AI/ML architectures. The student coming into this role will develop ML-based tools and flows to improve the PPA (Performance Power Area) and turnaround time for all aspects of chip implementation from synthesis to tapeout for various IPs. The work is done collaboratively with a group of highly experienced engineers across various domains of the ASIC.
This role is on-site, 40 hours, based out of Santa Clara, CA or Austin, TX.
Who You Are
- Currently pursuing a BS/MS/PhD in EE/ECE/CE/CS.
- Possessing deep knowledge of math, probability, statistics, and algorithms.
- Experienced in solving problems with Machine Learning models.
- Skilled in algorithms, data structures, and software development using Python and C/C++.
What We Need
- Ability to develop ML-based tools to improve PPA and turnaround time for chip implementation.
- Work closely with other PD engineers to develop ML tools for areas such as synthesis, PnR, timing closure, and power grid analysis.
- Responsibility for selecting appropriate datasets, data representation methods, and implementing new algorithms.
- Capability to run machine learning tests, perform statistical analysis, and fine-tune models using test results.
What You Will Learn
- How to apply ML systems and flows to high-performance designs for industry-leading AI/ML architectures.
- Practical experience in extending existing ML systems and implementing cutting-edge algorithms.
- Gain exposure to core physical design fundamentals, including synthesis, place and route, and timing analysis.
- Experience collaborating with a group of highly experienced engineers across various domains of the ASIC implementation.
Compensation for all interns at Tenstorrent ranges from $50/hr - $70/hr including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.
Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.