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Director Asic Design Jobs in Texas (NOW HIRING)

Ericsson GmbH

ASIC Design Verification Engineer

Austin, TX · On-site

$90 - $130/hr

  • Medical

  • Dental

  • Life

  • Retirement

  • PTO

ASIC Design Verification Engineer - Austin, Texas Hybrid work schedule. This is not a remote work ... Developing full test plans and directed/randomized test cases from scratch. * Object‑oriented ...

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Ericsson

ASIC Design Verification Engineer

Austin, TX · On-site

$134K - $164K/yr

  • Medical

  • Dental

  • Life

  • Retirement

  • PTO

ASIC Design Verification Engineer Austin, Texas This is not a remote work opportunity Hybrid work ... Experience developing full test plans and directed/randomized test cases from scratch Object ...

Ericsson

ASIC Design Verification Engineer

Austin, TX · On-site

$134K - $164K/yr

  • Medical

  • Dental

  • Life

  • Retirement

  • PTO

ASIC Design Verification Engineer Austin, Texas This is not a remote work opportunity Hybrid work ... Experience developing full test plans and directed/randomized test cases from scratch Object ...

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See Texas salary details

$33.9K

$123.3K

$180.7K

How much do director asic design jobs pay per year?

As of Aug 17, 2026, the average yearly pay for director asic design in Texas is $123,270.00, according to ZipRecruiter salary data. Most workers in this role earn between $96,300.00 and $152,300.00 per year, depending on experience, location, and employer.

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Director Asic Design jobs near you
Infographic showing various Director Asic Design job openings in Texas as of August 2026, with employment types broken down into 1% Internship, 89% Full Time, 6% Part Time, and 4% Contract. Highlights an 84% Physical, 5% Hybrid, and 11% Remote job distribution, with an average salary of $123,270 per year, or $59.3 per hour.

ASIC Design Verification Engineer

VentureSoft Global

Austin, TX • On-site

$134K - $164K/yr

Other

Posted 19 days ago

Job description

Job Title: Senior ASIC Design Verification Engineer
Location: Austin, TX / San Francisco, CA (Onsite/Hybrid)
 
Job Summary
 
We are seeking an experienced Senior ASIC Design Verification Engineer to verify next-generation CPU, AI/ML, and SoC designs. The ideal candidate will have strong expertise in developing UVM-based verification environments, functional coverage, RTL debug, and constrained-random verification while working closely with design and architecture teams from specification through tape-out.
 
Primary Skills (Must Have)
  • SystemVerilog & UVM
  • Constrained Random Verification (CRV)
  • Functional Coverage & Coverage Closure
  • RTL Debug & ASIC/SoC Verification
Key Responsibilities
  • Develop UVM/SystemVerilog verification environments.
  • Create test plans, testbenches, sequences, scoreboards, and checkers.
  • Perform block-level and full-chip ASIC/SoC verification.
  • Execute constrained-random and directed testing.
  • Debug RTL issues and drive functional coverage closure.
  • Collaborate with design, architecture, and validation teams.
  • Support regression, verification signoff, and tape-out activities.
Preferred Skills
  • CPU/Processor or Memory Subsystem Verification
  • SVA (SystemVerilog Assertions)
  • ARM, RISC, AI/ML Accelerator, or GPU verification
  • Experience with VCS, Questa, or Xcelium
  • Python or C/C++
Education
Bachelor''''''''s or Master''''''''s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
 

Thanks,

Vinutha

Venturesoft.ai

 

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