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Senior Asic Design Engineer Jobs in Texas (NOW HIRING)

Nvidia

Senior ASIC Floorplan Design Engineer

Austin, TX · On-site

We are now looking for a Senior ASIC Floorplan Design Engineer! NVIDIA is seeking a talented ASIC Floorplan Engineer to design and implement the world's leading SoC's and GPU's. This position offers ...

Cornelis Networks

PCIe ASIC Design Engineer

Austin, TX · On-site

Cornelis Networks is hiring a Senior ASIC Design Engineer to lead the design and integration of PCIe controllers into our next-generation SoCs. The ideal candidate will have deep expertise in PCI ...

InvestedintheMission

ASIC Design Engineer

Central, TX · On-site

$85 - $120/hr

Support the design and delivery of ASIC IP blocks from specification through RTL release under the guidance of senior engineers. * Assist in defining microarchitecture for digital signal-processing ...

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Nvidia

Senior ASIC Floorplan Design Engineer

Austin, TX · On-site

NVIDIA is seeking an experienced ASIC Floorplan Engineer to design and implement the world's leading SOCs, CPUs, and GPUs. This position offers you a unique opportunity to craft and to influence the ...

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Senior Asic Design Engineer information

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$130.4K

$165.5K

$204.5K

How much do senior asic design engineer jobs pay per year?

As of Aug 7, 2026, the average yearly pay for senior asic design engineer in Texas is $165,512.00, according to ZipRecruiter salary data. Most workers in this role earn between $148,100.00 and $181,700.00 per year, depending on experience, location, and employer.

What does a senior ASIC design engineer do?

A Senior ASIC Design Engineer is responsible for designing and developing Application-Specific Integrated Circuits (ASICs) used in a wide range of electronic devices. They lead the architecture, implementation, and verification of complex digital or mixed-signal circuits, often collaborating with cross-functional teams. This senior role involves optimizing designs for performance, power, and area while ensuring that the final product meets stringent technical and quality requirements. Additionally, they may mentor junior engineers and contribute to design methodologies and best practices within the organization.

What are the key skills and qualifications needed to thrive as a senior ASIC design engineer?

To thrive as a Senior ASIC Design Engineer, you need deep expertise in digital and/or analog circuit design, strong knowledge of hardware description languages (HDLs) like Verilog or VHDL, and a relevant engineering degree. Familiarity with EDA tools such as Synopsys, Cadence, and Mentor Graphics, as well as experience with simulation, synthesis, and verification methodologies, is typically required. Outstanding problem-solving, collaboration, and communication skills set top performers apart in this role. These competencies ensure efficient design cycles, robust chip functionality, and successful delivery of complex semiconductor projects.

What is the difference between Senior Asic Design Engineer vs Digital IC Design Engineer?

AspectSenior Asic Design EngineerDigital IC Design Engineer
Required CredentialsBachelor's/Master's in Electrical Engineering, VLSI, or related fields; experience in ASIC designBachelor's/Master's in Electrical Engineering, VLSI, or related fields; focus on digital circuit design
Work EnvironmentDesign teams in semiconductor or tech companies, hardware development labsIntegrated circuit design teams, research labs, semiconductor companies
Employer & Industry UsageUsed in ASIC development, FPGA design, hardware accelerationUsed in digital chip design, FPGA development, digital system integration

The main difference is that a Senior Asic Design Engineer specializes in designing application-specific integrated circuits, often leading complex projects, while a Digital IC Design Engineer focuses on digital circuit design within integrated circuits. Both roles require similar educational backgrounds and work environments but differ in project scope and specialization.

What are some common challenges senior ASIC design engineers face when collaborating with cross-functional teams?

Senior ASIC Design Engineers often work closely with verification, software, and systems teams throughout the development cycle. One common challenge is ensuring clear communication of design specifications and changes, as misunderstandings can lead to integration issues or delays. Balancing multiple project timelines and adapting to evolving requirements from other departments can also be demanding. Building strong, collaborative relationships and using robust documentation and project management tools are key to overcoming these challenges.
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Senior Asic Design Engineer jobs near you
Infographic showing various Senior Asic Design Engineer job openings in Texas as of July 2026, with employment types broken down into 92% Full Time, 6% Part Time, and 2% Contract. Highlights an 85% Physical, 4% Hybrid, and 11% Remote job distribution, with an average salary of $165,512 per year, or $79.6 per hour.

Senior ASIC Design Engineer

Cornelis Networks

Dallas, TX • On-site

Full-time

Medical, Dental, Vision, Life, Retirement, PTO

Re-posted 3 days ago

Job description

At Cornelis we're building the future of AI and HPC networking with an AI-first approach to silicon and software development. We're seeking engineers who are energized by working on cutting-edge ASIC design and distributed software systems, and who are motivated to push the boundaries on how AI can transform everything from chip architecture to system performance at scale.
Cornelis Networks delivers the world's highest performance scale-out networking solutions for AI and HPC datacenters. Our differentiated architecture seamlessly integrates hardware, software and system level technologies to maximize the efficiency of GPU, CPU and accelerator-based compute clusters at any scale. Our solutions drive breakthroughs in AI & HPC workloads, empowering our customers to push the boundaries of innovation. Backed by top-tier venture capital and strategic investors, we are committed to innovation, performance and scalability - solving the world's most demanding computational challenges with our next-generation networking solutions.
We are a fast-growing, forward-thinking team of architects, engineers, and business professionals with a proven track record of building successful products and companies. As a global organization, our team spans multiple U.S. states and six countries, and we continue to expand with exceptional talent in onsite, hybrid, and fully remote roles.
Cornelis Networks is seeking talented Senior ASIC Design Engineers with deep expertise in one or more of the critical areas needed to develop world-class SoCs for deployment in high-performance computing, advanced data analytics, and AI interconnect solutions. Ideal candidates will have relevant experience in the networking domain, with proven expertise in 50G, 100G, and 400G Ethernet protocols-including TCP/IP, RDMA/RoCE, and IPSec-and their application in high-speed data processing and networking environments.
Key Responsibilities:
  • Implement RTL designs using Verilog/System Verilog for high-speed data paths and packet processing logic.
  • Collaborate with verification engineers to create block- and system-level test plans to ensure comprehensive design coverage.
  • Define timing constraints for RTL blocks and work with Physical Design engineers to optimize timing closure.
  • Support post-silicon validation, collaborating with hardware, firmware, and software teams to debug and resolve ASIC issues.
  • Contribute to performance optimization and power-aware design strategies for Host Fabric Interface subsystems.

Minimum Qualifications:
  • B.S. or M.S. degree in Computer Engineering, Electrical Engineering, or related field.
  • 8+ years of post-college experience in digital design with proficiency in Verilog and System Verilog.
  • Experience in RTL design for high-speed data paths or packet processing in ASICs.
  • Deep understanding of Host Ethernet adaptor architectures.
  • Familiarity with timing closure and modern physical design methodologies.
  • Proven ability in system-level debug and root cause analysis of technical issues.
  • Strong verbal and written communication skills.

Preferred Qualifications:
  • Knowledge of Ethernet architecture and networking protocols.
  • Prior experience with RTL development for Ethernet host adapters and system debug.
  • Expertise in multiple clock domain designs and asynchronous interfaces.
  • 5+ years of experience with scripting languages such as TCL, Python, or Perl.
  • Familiarity with EDA tools like Design Compiler, Spyglass, or PrimeTime.

Location: This is a remote position for employees residing within the United States.
We offer a competitive compensation package that includes equity, cash, and incentives, along with health and retirement benefits. Our dynamic, flexible work environment provides the opportunity to collaborate with some of the most influential names in the semiconductor industry.
At Cornelis Networks your base salary is only one component of your comprehensive total rewards package. Your base pay will be determined by factors such as your skills, qualifications, experience, and location relative to the hiring range for the position. Depending on your role, you may also be eligible for performance-based incentives, including an annual bonus or sales incentives.
In addition to your base pay, you'll have access to a broad range of benefits, including medical, dental, and vision coverage, as well as disability and life insurance, a dependent care flexible spending account, accidental injury insurance, and pet insurance. We also offer generous paid holidays, 401(k) with company match, and Open Time Off (OTO) for regular full-time exempt employees. Other paid time off benefits include sick time, bonding leave, and pregnancy disability leave.
Cornelis Networks does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. Cornelis Networks is an equal opportunity employer, and all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity or expression, pregnancy, age, national origin, disability status, genetic information, protected veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.

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