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Asic Design Manager Jobs in Texas (NOW HIRING)

Meta is hiring an ASIC Design Verification Engineer within the Infrastructure Silicon organization ... management * Participate in design reviews and verification planning discussions to identify ...

As a Qualcomm ASIC Engineer, you will define, model, design (digital and/or analog), optimize ... architecture, product management, program management teams) to develop and execute an ...

ASIC Engineer, Design Responsibilities: * Develop micro-architecture, RTL coding, and design ... Experienced in managing SOC-level boot flow, Silicon Debug architectures and PLL/sequencing clocks ...

Senior ASIC Physical Design Engineer

Austin, TX ยท On-site

$165K - $241K/yr

Your Impact As a Physical Design Engineer, you will play a key role in the full RTL-to-GDSII ... Implement and manage timing ECO strategies using tools like Tweaker/PrimeTime. * Analyze quality ...

ASIC II - AMZ10244584

Austin, TX ยท On-site

$146K - $184K/yr

Offered Position: ASIC II Job Location: Austin, Texas Job Number: AMZ10244584 Position ... executive management, architects, and design leads on test strategy, yield optimization, and ...

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Asic Design Manager information

See Texas salary details

$39.1K

$106.7K

$187.7K

How much do asic design manager jobs pay per year?

As of Aug 8, 2026, the average yearly pay for asic design manager in Texas is $106,666.00, according to ZipRecruiter salary data. Most workers in this role earn between $77,800.00 and $134,200.00 per year, depending on experience, location, and employer.

Is ASIC design in demand?

ASIC design is in high demand due to the growth of industries such as consumer electronics, telecommunications, and automotive technology. Skilled ASIC design managers with expertise in hardware description languages and verification tools are sought after to develop custom integrated circuits for various applications.

What is the difference between Asic Design Manager vs Asic Design Engineer?

AspectAsic Design ManagerAsic Design Engineer
ResponsibilitiesOversees ASIC design projects, manages teams, and coordinates with stakeholdersPerforms ASIC design, coding, simulation, and verification tasks
Required SkillsLeadership, project management, ASIC design knowledgeHardware description languages, circuit design, verification skills
ExperienceTypically 8+ years in ASIC design, with leadership experienceUsually 2-5 years in ASIC design roles
Work EnvironmentDesign teams, project planning, cross-functional collaborationDesign labs, simulation environments, coding and testing

The main difference between an Asic Design Manager and an Asic Design Engineer lies in their roles. The manager oversees projects and teams, focusing on leadership and coordination, while the engineer concentrates on technical ASIC design and implementation. Both roles require ASIC design expertise, but the manager's role is more strategic and supervisory.

What are the key skills and qualifications needed to thrive as an ASIC Design Manager?

To thrive as an ASIC Design Manager, you need expertise in digital and analog ASIC design, project management experience, and typically a degree in electrical engineering or a related field. Familiarity with industry-standard EDA tools (such as Cadence or Synopsys), verification methodologies, and knowledge of relevant design flows is crucial. Strong leadership, communication, and problem-solving skills help manage teams and coordinate with cross-functional stakeholders. These competencies ensure high-quality chip designs are delivered on time and meet performance and cost targets, which is vital for organizational success.

Is ASIC design difficult?

ASIC design is a complex process that requires strong knowledge of digital logic, hardware description languages like VHDL or Verilog, and familiarity with electronic design automation tools. It involves multiple stages such as architecture, verification, and testing, making it challenging but manageable with proper training and experience.

What are some common challenges faced by an ASIC Design Manager in leading multidisciplinary teams?

ASIC Design Managers often navigate the complexities of coordinating multidisciplinary teams, including digital, analog, verification, and physical design engineers. One common challenge is ensuring clear communication across these specialties to maintain alignment on project goals, timelines, and technical requirements. Additionally, managing shifting priorities, resolving technical bottlenecks, and balancing resource allocation are frequent hurdles. Successful managers foster collaboration, set clear expectations, and leverage structured project management practices to keep teams productive and motivated.

What does an ASIC Design Manager do?

An ASIC Design Manager oversees the design and development of Application Specific Integrated Circuits (ASICs), managing a team of engineers through the entire chip design process. They coordinate project timelines, ensure technical specifications are met, and facilitate communication between design, verification, and manufacturing teams. Their role also involves resource planning, risk management, and ensuring that the final product meets performance, cost, and quality targets.
What are the most commonly searched types of Asic Design jobs in Texas? The most popular types of Asic Design jobs in Texas are:
What job categories do people searching Asic Design Manager jobs in Texas look for? The top searched job categories for Asic Design Manager jobs in Texas are:
What cities in Texas are hiring for Asic Design Manager jobs? Cities in Texas with the most Asic Design Manager job openings:
Infographic showing various Asic Design Manager job openings in Texas as of August 2026, with employment types broken down into 86% Full Time, 12% Part Time, and 2% Contract. Highlights an 86% Physical, 2% Hybrid, and 12% Remote job distribution, with an average salary of $106,666 per year, or $51.3 per hour.

Senior Manager, ASIC Design Engineering

Cornelis Networks

Austin, TX โ€ข On-site, Remote

Full-time

Medical, Dental, Vision, Life, Retirement, PTO

Re-posted 2 days ago


Job description

At Cornelis we're building the future of AI and HPC networking with an AI-first approach to silicon and software development. We're seeking engineers who are energized by working on cutting-edge ASIC design and distributed software systems, and who are motivated to push the boundaries on how AI can transform everything from chip architecture to system performance at scale.


At Cornelis we're building the future of AI and HPC networking with an AI-first approach to silicon and software development. We're seeking engineers who are energized by working on cutting-edge ASIC design and distributed software systems, and who are motivated to push the boundaries on how AI can transform everything from chip architecture to system performance at scale.


Cornelis Networks delivers the world's highest performance scale-out networking solutions for AI and HPC datacenters. Our differentiated architecture seamlessly integrates hardware, software and system level technologies to maximize the efficiency of GPU, CPU and accelerator-based compute clusters at any scale. Our solutions drive breakthroughs in AI & HPC workloads, empowering our customers to push the boundaries of innovation. Backed by top-tier venture capital and strategic investors, we are committed to innovation, performance and scalability - solving the world's most demanding computational challenges with our next-generation networking solutions.


We are a fast-growing, forward-thinking team of architects, engineers, and business professionals with a proven track record of building successful products and companies. As a global organization, our team spans multiple U.S. states and six countries, and we continue to expand with exceptional talent in onsite, hybrid, and fully remote roles.


Cornelis Networks islooking for aSenior ASIC Design Engineering Managerto lead and grow our RTL design engineering team.Reporting to the VP of ASIC Engineering,with direct exposure toexecutive leadership,this leaderwillmanagea team of talented design engineers anddrivefull-lifecycle development ofCornelis'next-generation, high-performance networking ASICs.The role isaccountable forbuilding and driving RTLimplementationschedules acrossallSoC subsystemsand full-chipmilestones. Successrequiresdeep hands-onexpertisein advanced RTL designimplementation,methodologies,and SoC flows,from microarchitecturedefinitionthroughRTL delivery,tape-outreadiness, andcross-functionalexecutionwith Architecture, DesignVerification, Emulation,andPhysical Design.This leaderwill alsoownheadcount planning,hiring,and organizationalstrategyto build animble, efficient,world-classdesign team.Exposureto AI-based design flowsandmethodologyispreferred.


This role isintendedfor a senior engineering leader who can combine hands-on ASIC RTL designexpertisewith disciplined program execution, cross-functional coordination, andteam buildingat scale.


Key Responsibilities

  • OwnASIC RTL delivery schedules across major milestonesbytracking,monitoring,and reportingprogress against committedplans.
  • Utilize data-driven insights to predictschedulerisks and proactively reallocate human resources to keep the project on track.
  • AlignRTL delivery scheduleswith DV andemulationenablement andmanagefeedbackloopsand dependencies efficiently.
  • Facilitatephysical designhandoffsbyensuringdesign teams provide high-quality RTL and constraintsthatminimize timing-closure iterations. Track physical design feedback anddelivery schedules to support physical designsignoff and tape-out milestones.
  • Leadlong-term headcount planning and organizationaldesignfor the ASIC department.Identifyskill gaps and executeglobal talent acquisition strategiesthat support theproduct roadmap.

MinimumQualifications

  • 15+ years in the semiconductor industry,preferably inhigh performancedesigns on advanced technology nodes,with at least5years in people management
  • B.S. or M.S. in Computer Engineering, Electrical Engineering, or related technical field, or equivalent practical experience
  • Deep understanding of the interaction between Design, Verification, Emulation, and Physical Design teams. You must know "how the work gets done" to manage the people doing it.
  • Proven ability to lead largeengineering organizations through multiple full-cycle ASIC product launchesin a remoteenvironment.Ability to coordinate across multiple projects, manage risks and escalations, and work under tight schedules and budget constraints.
  • Strong technicalexpertisein microarchitecture development, RTL coding (Verilog/SystemVerilog), synthesis, STA/timing closure, physical design, and verification methodologies.
  • Exposuretoone or more industry standards/protocol stacks such as PCIe, Ethernet, UCIe,UALink.
  • Demonstrated ability tooptimizedesigns for PPA (power, performance, area) and to integrate major subsystems (interconnect, I/O, memory).


Preferred Qualifications

  • Exposure to AI based design implementation and verification flows, scripting for automation, milestonetrackingand flow integration
  • Experience building globally distributed ASIC design teams and scaling engineering practicesin a remote environment.


Location:This is a remote position for employees residing within the United States.


We offer a competitive compensation package that includes equity, cash, and incentives, along with health and retirement benefits. Our dynamic, flexible work environment provides the opportunity to collaborate with some of the most influential names in the semiconductor industry.


At Cornelis Networks your base salary is only one component of your comprehensive total rewards package. Your base pay will be determined by factors such as your skills, qualifications, experience, and location relative to the hiring range for the position. Depending on your role, you may also be eligible for performance-based incentives, including an annual bonus or sales incentives.


In addition to your base pay, you'll have access to a broad range of benefits, including medical, dental, and vision coverage, as well as disability and life insurance, a dependent care flexible spending account, accidental injury insurance, and pet insurance. We also offer generous paid holidays, 401(k) with company match, and Open Time Off (OTO) for regular full-time exempt employees. Other paid time off benefits include sick time, bonding leave, and pregnancy disability leave.


Cornelis Networks does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. Cornelis Networks is an equal opportunity employer, and all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity or expression, pregnancy, age, national origin, disability status, genetic information, protected veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.