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Asic Design Manager Jobs in Texas (NOW HIRING)

Meta

ASIC Engineer, Design Verification

Austin, TX · On-site +1

$114K/yr

Meta is hiring an ASIC Design Verification Engineer within the Infrastructure Silicon organization ... management * Participate in design reviews and verification planning discussions to identify ...

Meta

ASIC Engineer, Design

Austin, TX

$146K/yr

ASIC Engineer, Design Responsibilities: * Develop micro-architecture, RTL coding, and design ... Experienced in managing SOC-level boot flow, Silicon Debug architectures and PLL/sequencing clocks ...

Cisco

Senior ASIC Physical Design Engineer

Austin, TX · On-site

$165K - $241K/yr

Your Impact As a Physical Design Engineer, you will play a key role in the full RTL-to-GDSII ... Implement and manage timing ECO strategies using tools like Tweaker/PrimeTime. * Analyze quality ...

Amazon

ASIC II - AMZ10244584

Austin, TX · On-site

$146K - $184K/yr

Offered Position: ASIC II Job Location: Austin, Texas Job Number: AMZ10244584 Position ... executive management, architects, and design leads on test strategy, yield optimization, and ...

Apple

Timing Design Engineer

Austin, TX · On-site

Description As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC ... constraints generation and management, proficient in scripting languages (Tcl and Perl ...

Apple

Timing Design Engineer

Austin, TX

Description As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC ... Hands on experience in timing/SDC constraints generation and management. Proficient in scripting ...

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All JobsAsic Design JobsAsic Design Manager JobsAsic Design Manager Jobs in Texas

Asic Design Manager information

See Texas salary details

$39.1K

$106.7K

$187.7K

How much do asic design manager jobs pay per year?

As of Aug 3, 2026, the average yearly pay for asic design manager in Texas is $106,666.00, according to ZipRecruiter salary data. Most workers in this role earn between $77,800.00 and $134,200.00 per year, depending on experience, location, and employer.

Is ASIC design in demand?

ASIC design is in high demand due to the growth of industries such as consumer electronics, telecommunications, and automotive technology. Skilled ASIC design managers with expertise in hardware description languages and verification tools are sought after to develop custom integrated circuits for various applications.

What is the difference between Asic Design Manager vs Asic Design Engineer?

AspectAsic Design ManagerAsic Design Engineer
ResponsibilitiesOversees ASIC design projects, manages teams, and coordinates with stakeholdersPerforms ASIC design, coding, simulation, and verification tasks
Required SkillsLeadership, project management, ASIC design knowledgeHardware description languages, circuit design, verification skills
ExperienceTypically 8+ years in ASIC design, with leadership experienceUsually 2-5 years in ASIC design roles
Work EnvironmentDesign teams, project planning, cross-functional collaborationDesign labs, simulation environments, coding and testing

The main difference between an Asic Design Manager and an Asic Design Engineer lies in their roles. The manager oversees projects and teams, focusing on leadership and coordination, while the engineer concentrates on technical ASIC design and implementation. Both roles require ASIC design expertise, but the manager's role is more strategic and supervisory.

What are the key skills and qualifications needed to thrive as an ASIC Design Manager?

To thrive as an ASIC Design Manager, you need expertise in digital and analog ASIC design, project management experience, and typically a degree in electrical engineering or a related field. Familiarity with industry-standard EDA tools (such as Cadence or Synopsys), verification methodologies, and knowledge of relevant design flows is crucial. Strong leadership, communication, and problem-solving skills help manage teams and coordinate with cross-functional stakeholders. These competencies ensure high-quality chip designs are delivered on time and meet performance and cost targets, which is vital for organizational success.

Is ASIC design difficult?

ASIC design is a complex process that requires strong knowledge of digital logic, hardware description languages like VHDL or Verilog, and familiarity with electronic design automation tools. It involves multiple stages such as architecture, verification, and testing, making it challenging but manageable with proper training and experience.

What are some common challenges faced by an ASIC Design Manager in leading multidisciplinary teams?

ASIC Design Managers often navigate the complexities of coordinating multidisciplinary teams, including digital, analog, verification, and physical design engineers. One common challenge is ensuring clear communication across these specialties to maintain alignment on project goals, timelines, and technical requirements. Additionally, managing shifting priorities, resolving technical bottlenecks, and balancing resource allocation are frequent hurdles. Successful managers foster collaboration, set clear expectations, and leverage structured project management practices to keep teams productive and motivated.

What does an ASIC Design Manager do?

An ASIC Design Manager oversees the design and development of Application Specific Integrated Circuits (ASICs), managing a team of engineers through the entire chip design process. They coordinate project timelines, ensure technical specifications are met, and facilitate communication between design, verification, and manufacturing teams. Their role also involves resource planning, risk management, and ensuring that the final product meets performance, cost, and quality targets.
What are the most commonly searched types of Asic Design jobs in Texas? The most popular types of Asic Design jobs in Texas are:
What are popular job titles related to Asic Design Manager jobs in Texas? For Asic Design Manager jobs in Texas, the most frequently searched job titles are:
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Asic Design Manager jobs near you
Infographic showing various Asic Design Manager job openings in Texas as of July 2026, with employment types broken down into 20% As Needed, 73% Full Time, 4% Part Time, 2% Contract, and 1% Summer. Highlights an 85% Physical, 9% Hybrid, and 6% Remote job distribution, with an average salary of $106,666 per year, or $51.3 per hour.

ASIC Engineer, Design Verification

Meta

Austin, TX • On-site, Remote

$114K/yr

Full-time

Re-posted 2 days ago

Meta rating

7.8

Company rating: 7.8 out of 10

Based on 45 frontline employees who took The Breakroom Quiz

135th of 241 rated software companies

Job description

Meta is hiring an ASIC Design Verification Engineer within the Infrastructure Silicon organization. We are looking for individuals with experience in Design Verification to build IP and System on Chip (SoC) solutions for data center applications.In this role, you will work alongside experienced engineers focused on developing advanced ASIC solutions that power Meta's data center infrastructure. You will own verification closure for design modules or sub-systems, spanning test planning, UVM-based testbench development, and coverage closure. In addition to simulation-based verification, you will leverage formal verification and emulation methodologies to achieve bug-free silicon. This role offers meaningful opportunities to collaborate with full-stack software, hardware, ASIC design, emulation, and post-silicon validation teams toward first-pass silicon success.
ASIC Engineer, Design Verification Responsibilities:
  • Define and implement block, IP, and SoC-level verification plans to enable comprehensive functional coverage across design hierarchies
  • Develop and maintain UVM-based testbenches and functional test sequences aligned to the verification test plan
  • Drive verification closure using defined metrics including functional coverage, code coverage, and assertion coverage
  • Debug and root-cause functional failures in RTL designs, partnering closely with the ASIC design team to resolve issues
  • Apply formal verification and emulation techniques to complement simulation-based approaches and improve verification efficiency
  • Collaborate with design, architecture, and post-silicon validation teams to align on verification goals and ensure design quality
  • Develop reusable verification infrastructure components including scoreboards, monitors, and coverage models
  • Contribute to scripting and automation flows using Python, TCL, or Shell to improve verification productivity and regression management
  • Participate in design reviews and verification planning discussions to identify potential design risks early in the development cycle

Minimum Qualifications:
  • Currently has, or is in the process of obtaining a Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience. Degree must be completed prior to joining Meta
  • 2+ years of hands-on experience in SystemVerilog and UVM-based verification methodology or C/C++ based hardware verification
  • 2+ years of experience in block, IP, sub-system, or SoC-level verification using SystemVerilog UVM or OVM methodologies
  • Experience with EDA simulation tools and scripting languages such as Python, TCL, Perl, or Shell for building verification environments and flows
  • Experience debugging RTL functional failures and performing root-cause analysis in a simulation or emulation environment

Preferred Qualifications:
  • Experience with Emulation platform usage for Pre-Si verification
  • Experience verifying ARM or RISC-V based sub-systems or SoCs, or data center application designs such as AI/ML accelerators, networking, or video processing ASICs
  • Experience with IP or integration verification of high-speed interfaces such as PCIe, DDR, or Ethernet
  • Experience developing UVM-based verification environments from scratch, including environment architecture, sequencers, and coverage models
  • Experience with Chip Debug Logic, Telemetry and/or RAS

About Meta:
Meta builds technologies that help people connect, find communities, and grow businesses. When Facebook launched in 2004, it changed the way people connect. Apps like Messenger, Instagram and WhatsApp further empowered billions around the world. Now, Meta is moving beyond 2D screens toward immersive experiences like augmented and virtual reality to help build the next evolution in social technology. People who choose to build their careers by building with us at Meta help shape a future that will take us beyond what digital connection makes possible today—beyond the constraints of screens, the limits of distance, and even the rules of physics.
Meta is proud to be an Equal Employment Opportunity and Affirmative Action employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender, gender identity, gender expression, transgender status, sexual stereotypes, age, status as a protected veteran, status as an individual with a disability, or other applicable legally protected characteristics. We also consider qualified applicants with criminal histories, consistent with applicable federal, state and local law. Meta participates in the E-Verify program in certain locations, as required by law. Please note that Meta may leverage artificial intelligence and machine learning technologies in connection with applications for employment.
Meta is committed to providing reasonable accommodations for candidates with disabilities in our recruiting process. If you need any assistance or accommodations due to a disability, please let us know at accommodations-ext@meta.com.
$114,000/year to $172,000/year + bonus + equity + benefits
Individual compensation is determined by skills, qualifications, experience, and location. Compensation details listed in this posting reflect the base hourly rate, monthly rate, or annual salary only, and do not include bonus, equity or sales incentives, if applicable. In addition to base compensation, Meta offers benefits. Learn more about benefits at Meta.

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