Austin, TX · On-site
$115.60 - $173.40/hr
Manage tapeout activities, ensuring sign‑off for DRC, LVS, timing, power integrity, and ... Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design ...
Austin, TX · On-site
$115.60 - $173.40/hr
Manage tapeout activities, ensuring sign‑off for DRC, LVS, timing, power integrity, and ... Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design ...
Austin, TX · On-site
Description As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC ... constraints generation and management, proficient in scripting languages (Tcl and Perl ...
Austin, TX · On-site
Description As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC ... constraints generation and management, proficient in scripting languages (Tcl and Perl ...
Description As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC ... Hands on experience in timing/SDC constraints generation and management. Proficient in scripting ...
Description As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC ... Hands on experience in timing/SDC constraints generation and management. Proficient in scripting ...
Plano, TX · On-site
$130K - $158K/yr
and other details - We are seeking an ASIC Design Verification Engineer whose role will be to ... Manage regression testing, simulation farms, and CI pipelines to ensure high test throughput and ...
Quick apply
Plano, TX · On-site
$130K - $158K/yr
and other details - We are seeking an ASIC Design Verification Engineer whose role will be to ... Manage regression testing, simulation farms, and CI pipelines to ensure high test throughput and ...
Austin, TX · On-site
Description As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC ... Hands on experience in timing/SDC constraints generation and management. Proficient in scripting ...
Austin, TX · On-site
Description As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC ... Hands on experience in timing/SDC constraints generation and management. Proficient in scripting ...
Description As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC ... constraints generation and management, proficient in scripting languages (Tcl and Perl ...
Description As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC ... constraints generation and management, proficient in scripting languages (Tcl and Perl ...
$117K - $161K/yr
Design documentation and configuration management are required. What You Will Do * Design and ... FPGA/ASIC design, including VHDL and/or Verilog coding or FPGA/ASIC verification using ...
$117K - $161K/yr
Design documentation and configuration management are required. What You Will Do * Design and ... FPGA/ASIC design, including VHDL and/or Verilog coding or FPGA/ASIC verification using ...
$121K - $168K/yr
Design documentation and configuration management are required. What You Will Do * Design and ... FPGA/ASIC design, including VHDL and/or Verilog coding or FPGA/ASIC verification using ...
$121K - $168K/yr
Design documentation and configuration management are required. What You Will Do * Design and ... FPGA/ASIC design, including VHDL and/or Verilog coding or FPGA/ASIC verification using ...
$121K - $167K/yr
Design documentation and configuration management are required. What You Will Do * Design and ... FPGA/ASIC design, including VHDL and/or Verilog coding or FPGA/ASIC verification using ...
$121K - $167K/yr
Design documentation and configuration management are required. What You Will Do * Design and ... FPGA/ASIC design, including VHDL and/or Verilog coding or FPGA/ASIC verification using ...
$111K - $153K/yr
Design documentation and configuration management are required. What You Will Do * Design and ... FPGA/ASIC design, including VHDL and/or Verilog coding or FPGA/ASIC verification using ...
$111K - $153K/yr
Design documentation and configuration management are required. What You Will Do * Design and ... FPGA/ASIC design, including VHDL and/or Verilog coding or FPGA/ASIC verification using ...
... ASIC implementations in Verilog/SystemVerilog • Run formal verification of complex blocks to ... manage stress and work safely and respectfully with others, exhibit trustworthiness and ...
... ASIC implementations in Verilog/SystemVerilog • Run formal verification of complex blocks to ... manage stress and work safely and respectfully with others, exhibit trustworthiness and ...
The ideal candidate brings strong hands-on STA expertise, deep understanding of ASIC design flows ... managing latency and skew tradeoffs, and applying timing budgeting, derating, and multi-voltage ...
The ideal candidate brings strong hands-on STA expertise, deep understanding of ASIC design flows ... managing latency and skew tradeoffs, and applying timing budgeting, derating, and multi-voltage ...
... managing latency and skew tradeoffs, and applying timing budgeting, derating, and multi-voltage ... D. 7+ years of hands-on experience with ASIC design flows and electrical engineering fundamentals.
... managing latency and skew tradeoffs, and applying timing budgeting, derating, and multi-voltage ... D. 7+ years of hands-on experience with ASIC design flows and electrical engineering fundamentals.
Austin, TX · On-site
We're looking for an ASIC Design Eengineer to help us trail-blaze new technologies and architectures, while ensuring high design quality and making the right trade-offs. Our team is dedicated to ...
Austin, TX · On-site
We're looking for an ASIC Design Eengineer to help us trail-blaze new technologies and architectures, while ensuring high design quality and making the right trade-offs. Our team is dedicated to ...
Grand Prairie, TX · On-site
$88.99/hr
Engineering - ASIC & FPGA Design Engineering | Grand Prairie, Texas, United States Job Summary ... and manage comprehensive design documentation. - Lead synthesis, place and route, and timing ...
Grand Prairie, TX · On-site
$88.99/hr
Engineering - ASIC & FPGA Design Engineering | Grand Prairie, Texas, United States Job Summary ... and manage comprehensive design documentation. - Lead synthesis, place and route, and timing ...
Austin, TX · Remote
$137K - $168K/yr
Develop RTL design code and simulation in VHDL, Verilog, and/or SystemVerilog. * Create UVM ... Communicate well with a wide variety of individuals including Engineering, Program Management ...
Austin, TX · Remote
$137K - $168K/yr
Develop RTL design code and simulation in VHDL, Verilog, and/or SystemVerilog. * Create UVM ... Communicate well with a wide variety of individuals including Engineering, Program Management ...
We're looking for an ASIC Design Eengineer to help us trail-blaze new technologies and architectures, while ensuring high design quality and making the right trade-offs. Our team is dedicated to ...
We're looking for an ASIC Design Eengineer to help us trail-blaze new technologies and architectures, while ensuring high design quality and making the right trade-offs. Our team is dedicated to ...
We are now looking for a motivated Senior ASIC Physical Design Engineer, Netlisting to join our ... management, and ECO generation and implementation. What we need to see: * BS (or equivalent ...
We are now looking for a motivated Senior ASIC Physical Design Engineer, Netlisting to join our ... management, and ECO generation and implementation. What we need to see: * BS (or equivalent ...
Grand Prairie, TX · On-site
$88.99/hr
Manage configuration control using GitLab (or equivalent), maintain version controlled repositories ... Experience in full ASIC/FPGA lifecycle (architecture, design, simulation, verification, validation ...
Grand Prairie, TX · On-site
$88.99/hr
Manage configuration control using GitLab (or equivalent), maintain version controlled repositories ... Experience in full ASIC/FPGA lifecycle (architecture, design, simulation, verification, validation ...
Design documentation and configuration management are required. This position is 100% ONSITE in ... FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (SystemVerilog coding)
Design documentation and configuration management are required. This position is 100% ONSITE in ... FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (SystemVerilog coding)
$39.1K - $52.6K
4% of jobs
$52.6K - $66.1K
8% of jobs
$76.1K is the 25th percentile. Wages below this are outliers.
$66.1K - $79.7K
17% of jobs
The median wage is $92.2K / yr.
$79.7K - $93.2K
22% of jobs
$93.2K - $106.7K
15% of jobs
$106.7K - $120.2K
6% of jobs
$124.5K is the 75th percentile. Wages above this are outliers.
$120.2K - $133.7K
7% of jobs
$133.7K - $147.2K
7% of jobs
$147.2K - $160.7K
8% of jobs
$160.7K - $174.2K
2% of jobs
$174.2K - $187.7K
2% of jobs
$39.1K
$106.7K
$187.7K
| Aspect | Asic Design Manager | Asic Design Engineer |
|---|---|---|
| Responsibilities | Oversees ASIC design projects, manages teams, and coordinates with stakeholders | Performs ASIC design, coding, simulation, and verification tasks |
| Required Skills | Leadership, project management, ASIC design knowledge | Hardware description languages, circuit design, verification skills |
| Experience | Typically 8+ years in ASIC design, with leadership experience | Usually 2-5 years in ASIC design roles |
| Work Environment | Design teams, project planning, cross-functional collaboration | Design labs, simulation environments, coding and testing |
The main difference between an Asic Design Manager and an Asic Design Engineer lies in their roles. The manager oversees projects and teams, focusing on leadership and coordination, while the engineer concentrates on technical ASIC design and implementation. Both roles require ASIC design expertise, but the manager's role is more strategic and supervisory.
$115.60 - $173.40/hr
Other
Re-posted 8 days ago
8.8
Based on 11 frontline employees who took The Breakroom Quiz
51st of 242 rated software companies
QCT’s DSP Team is actively seeking talented Physical Design Engineers to join our DSP PD team. As a Physical Design Engineer, you will innovate, develop, and implement DSP cores using state‑of‑the‑art tools and technologies. This role requires strong expertise in physical design flow, tapeout readiness, and Power, Performance, and Area (PPA) optimization for advanced technology nodes. Backfill.
Key ResponsibilitiesQualcomm is an equal opportunity employer; all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or any other protected classification.
Accessibility and AccommodationsIf you are an individual with a disability and need an accommodation during the application/hiring process, Qualcomm is committed to providing an accessible process. Please email disability‑accommodations@qualcomm.com or call Qualcomm’s toll‑free number for assistance.
CompensationPay range: $115,600.00 – $173,400.00. In addition, Qualcomm offers a competitive annual discretionary bonus program and opportunities for annual RSU grants.
Sourced by ZipRecruiter
Qualcomm is enabling a world where everyone and everything can be intelligently connected. You interact with products and technologies made possible by Qualcomm every day, including 5G-enabled smartphones that double as pro-level cameras and gaming devices, smarter vehicles and cities, and the technology behind the smart, connected factories that manufactured your latest purchase. Our powerful connectivity solutions keep you connected—even in remote areas. Qualcomm 5G and AI innovations are the power behind the connected intelligent edge. You’ll find our technologies behind and inside the innovations that deliver significant value across multiple industries and to billions of people every day.
Technology, communication and media
10,000+ Employees
San Diego, CA, US
1985
