ZipRecruiter

Log In

1

Asic Design Intern Jobs (NOW HIRING)

Ambarella

Logic design, implementation, and verification using Verilog, System Verilog, and any required programing and scripting languages. * Synthesize and optimize RTL for timing, area and power.

Etched

PD Intern

San Jose, CA · On-site

Job Summary As a Physical Design intern for Etched, you will be responsible for realizing our ... Exposure to ASIC or SoC design concepts * Familiarity with SystemVerilog, UVM, or Python

Etched

PD Intern

San Jose, CA · On-site

Job Summary As a Physical Design intern for Etched, you will be responsible for realizing our ... Exposure to ASIC or SoC design concepts * Familiarity with SystemVerilog, UVM, or Python

Etched

SI/PI Intern

San Jose, CA · On-site

Job Summary As a Signal Integrity / Power Integrity Intern, you will help design and validate the next generation of high-performance AI systems. You will work closely with package, PCB, ASIC, and ...

Etched

SI/PI Intern

San Jose, CA · On-site

Job Summary As a Signal Integrity / Power Integrity Intern, you will help design and validate the next generation of high-performance AI systems. You will work closely with package, PCB, ASIC, and ...

SAAZ Micro Inc

Digital IC Design Intern

Camarillo, CA · On-site

$5.0K/mo

Must have experience with digital IC design, methodology, and tools. Should be able to work ... ASIC platforms. Should be able to work with processors, develop algorithms, and optimize ...

SAAZ Micro Inc

Digital IC Design Intern

Camarillo, CA · On-site

$5.0K/mo

Must have experience with digital IC design, methodology, and tools. Should be able to work ... ASIC platforms. Should be able to work with processors, develop algorithms, and optimize ...

Etched

DFT Intern

San Jose, CA · On-site

$17.50 - $23.50/hr

Job Summary As a DFT Intern at Etched, you will help review and refine DFT flow automation to ... Exposure to ASIC or SoC design concepts * Familiarity with digital logic design fundamentals

Etched

RTL Intern

San Jose, CA · On-site

Job Summary As an RTL Intern at Etched, you will help design microarchitecture and implement logic ... Exposure to ASIC or SoC design concepts * Familiarity with SystemVerilog, UVM, or Python

Etched

DFT Intern

San Jose, CA · On-site

$17.50 - $23.50/hr

Job Summary As a DFT Intern at Etched, you will help review and refine DFT flow automation to ... Exposure to ASIC or SoC design concepts * Familiarity with digital logic design fundamentals

next page

Showing results 1-20

All JobsAsic Design Intern Jobs

Asic Design Intern information

See salary details

$9

$19

$36

How much do asic design intern jobs pay per hour?

As of Jul 18, 2026, the average hourly pay for asic design intern in the United States is $19.38, according to ZipRecruiter salary data. Most workers in this role earn between $14.42 and $21.63 per hour, depending on experience, location, and employer.

What is an ASIC Design Intern job?

An ASIC Design Intern assists in the design, verification, and testing of Application-Specific Integrated Circuits (ASICs). Interns work with experienced engineers to develop digital or analog circuit designs, run simulations, and debug hardware issues. They gain hands-on experience with design tools, scripting languages, and verification methodologies. This role provides valuable industry exposure and helps interns build skills in VLSI, RTL design, and semiconductor development.

What are the key skills and qualifications needed to thrive in the Asic Design Intern position, and why are they important?

To thrive as an ASIC Design Intern, you need a solid foundation in digital logic design, computer architecture, and proficiency with hardware description languages such as Verilog or VHDL, typically supported by coursework in electrical or computer engineering. Familiarity with industry-standard EDA tools like Cadence or Synopsys and experience with simulation and debugging environments are highly valued. Strong problem-solving skills, attention to detail, and effective communication make you stand out in collaborative team projects. These skills ensure you can contribute effectively to complex design tasks, learn quickly, and integrate seamlessly into professional ASIC development teams.

What are the typical responsibilities of an ASIC Design Intern during their internship?

As an ASIC Design Intern, your responsibilities may include assisting with the design and verification of digital circuits, creating testbenches, running simulations, and helping debug hardware issues alongside experienced engineers. You may also document design processes, participate in reviews, and contribute to tool flow development or optimization tasks. Interns often work closely with senior design, verification, and physical design engineers, gaining exposure to a variety of stages in the ASIC development lifecycle. This hands-on experience not only builds your technical expertise but also helps you develop teamwork and project management skills, which are essential for advancing in hardware engineering roles.

More about Asic Design Intern jobs
What cities are hiring for Asic Design Intern jobs? Cities with the most Asic Design Intern job openings:
What are the most commonly searched types of Asic Design jobs? The most popular types of Asic Design jobs are:
What states have the most Asic Design Intern jobs? States with the most job openings for Asic Design Intern jobs include:
What job categories do people searching Asic Design Intern jobs look for? The top searched job categories for Asic Design Intern jobs are:
Asic Design Intern jobs near you
Infographic showing various Asic Design Intern job openings in the United States as of July 2026, with employment types broken down into 95% Full Time, 1% Part Time, 2% Contract, and 2% Summer. Highlights an 89% Physical, 6% Hybrid, and 5% Remote job distribution, with an average salary of $40,304 per year, or $19.4 per hour.
Physical Design Intern

Physical Design Intern

SK hynix memory solutions America Inc.

San Jose, CA • On-site

$35 - $45/hr

Internship

Posted 19 days ago

Job description

About the Company:
At SK Hynix Memory Solution, we're at the forefront of semiconductor innovation, developing advanced memory solutions that power everything from smartphones to data centers. As a global leader in DRAM and NAND flash technologies, we drive the evolution of advancing mobile technology, empowering cloud computing, and pioneering future technologies. Our cutting-edge memory technologies are essential in today's most advanced electronic devices and IT infrastructure, enabling enhanced performance and user experiences across the digital landscape.
We're looking for innovative minds to join our mission of shaping the future of technology. At SK Hynix Memory, you'll be part of a team that's pioneering breakthrough memory solutions while maintaining a strong commitment to sustainability. We're not just adapting to technological change - we're driving it, with significant investments in artificial intelligence, machine learning, and eco-friendly solutions and operational practices. As we continue to expand our market presence and push the boundaries of what's possible in semiconductor technology, we invite you to be part of our journey to creating the next generation of memory solutions that will define the future of computing.
About the Role: Join our Physical Design team to help deliver next-generation SSD controller chips. As a Physical Design Intern, you will collaborate with experienced engineers to transform RTL designs into functional physical layouts. You will gain hands-on experience in the complete ASIC flow from synthesis to tape-out, working on real projects in a fast-paced, innovative environment.
Responsibilities:
  • Execute ASIC physical design implementation flows, including floorplanning, placement, clock tree synthesis (CTS), and routing.
  • Perform static timing analysis (STA) and work to resolve setup and hold timing violations.
  • Run and analyze design rule checks (DRC) and layout versus schematic (LVS) checks to ensure design integrity, as well as IR-Drop analysis.
  • Assist in optimizing power, performance, and area (PPA) metrics using industry-standard EDA tools.
  • Developing entire P&R/physical verification/IR-EM flows.
  • Collaborate with front-end design and verification teams to seamlessly integrate RTL changes and resolve physical design constraints.
  • Help generate and maintain physical design scripts, utilities, and documentation for the team.

Minimum Qualifications:
  • Currently pursuing a Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.
  • Foundational understanding of VLSI design concepts, CMOS circuit design, and digital logic.
  • Familiarity with the basic stages of the ASIC physical design flow.
  • Academic or project experience with scripting languages such as Python, Perl, or TCL.
  • Strong analytical and problem-solving skills with a high attention to detail.

Preferred Qualifications:
  • Hands-on coursework or project experience with industry-standard EDA tools (e.g., Synopsys ICC2, Cadence Innovus, or similar).
  • Exposure to Static Timing Analysis (STA) concepts and tools (e.g., PrimeTime, Tempus).
  • Basic understanding of design constraints (SDC) and library exchange formats (LEF/DEF).
  • Knowledge of low-power design techniques and power intent formats (UPF/CPF).
  • Familiarity with AI/LLM tools (e.g., GPT, Copilot) and prompt engineering, with the ability to leverage them to automate EDA scripting, analyze design data, or optimize workflows.

COMPENSATION: $35/hr - $45/hr

Apply