ASIC Design Intern
Beaverton, OR ยท On-site
We are seeking a motivated ASIC Design Intern (Co-op or Internship) to join our engineering team during the summer term. This role is designed for students who are eager to gain hands-on experience ...
Beaverton, OR ยท On-site
We are seeking a motivated ASIC Design Intern (Co-op or Internship) to join our engineering team during the summer term. This role is designed for students who are eager to gain hands-on experience ...
Beaverton, OR ยท On-site
We are seeking a motivated ASIC Design Intern (Co-op or Internship) to join our engineering team during the summer term. This role is designed for students who are eager to gain hands-on experience ...
$35 - $45/hr
This team spans the full design cycle--from micro-architecture and RTL design to timing closure and tapeout readiness--enabling next-generation enterprise and AI data center storage solutions.
Quick apply
$35 - $45/hr
This team spans the full design cycle--from micro-architecture and RTL design to timing closure and tapeout readiness--enabling next-generation enterprise and AI data center storage solutions.
$35 - $45/hr
This team spans the full design cycle-from micro-architecture and RTL design to timing closure and tapeout readiness-enabling next-generation enterprise and AI data center storage solutions.
$35 - $45/hr
This team spans the full design cycle-from micro-architecture and RTL design to timing closure and tapeout readiness-enabling next-generation enterprise and AI data center storage solutions.
San Jose, CA ยท On-site
$35 - $45/hr
This team spans the full design cycle-from micro-architecture and RTL design to timing closure and tapeout readiness-enabling next-generation enterprise and AI data center storage solutions.
San Jose, CA ยท On-site
$35 - $45/hr
This team spans the full design cycle-from micro-architecture and RTL design to timing closure and tapeout readiness-enabling next-generation enterprise and AI data center storage solutions.
$35 - $45/hr
Willingness to learn ASIC design flows, tools, and methodologies. * Strong attention to detail and ability to follow structured workflows. Preferred Qualifications * Introductory exposure to DFT ...
Quick apply
$35 - $45/hr
Willingness to learn ASIC design flows, tools, and methodologies. * Strong attention to detail and ability to follow structured workflows. Preferred Qualifications * Introductory exposure to DFT ...
San Jose, CA ยท On-site
$35 - $45/hr
Willingness to learn ASIC design flows, tools, and methodologies. * Strong attention to detail and ability to follow structured workflows. Preferred Qualifications * Introductory exposure to DFT ...
San Jose, CA ยท On-site
$35 - $45/hr
Willingness to learn ASIC design flows, tools, and methodologies. * Strong attention to detail and ability to follow structured workflows. Preferred Qualifications * Introductory exposure to DFT ...
$35 - $45/hr
Willingness to learn ASIC design flows, tools, and methodologies. * Strong attention to detail and ability to follow structured workflows. Preferred Qualifications * Introductory exposure to DFT ...
$35 - $45/hr
Willingness to learn ASIC design flows, tools, and methodologies. * Strong attention to detail and ability to follow structured workflows. Preferred Qualifications * Introductory exposure to DFT ...
Logic design, implementation, and verification using Verilog, System Verilog, and any required programing and scripting languages. * Synthesize and optimize RTL for timing, area and power.
Logic design, implementation, and verification using Verilog, System Verilog, and any required programing and scripting languages. * Synthesize and optimize RTL for timing, area and power.
San Jose, CA ยท On-site
$159K/yr
Participate in the ASIC/SoC design flow , including RTL development, verification, and system ... Student / Intern (Fixed Term) Shift: Shift 1 (United States of America) Primary Location: San Jose ...
New
San Jose, CA ยท On-site
$159K/yr
Participate in the ASIC/SoC design flow , including RTL development, verification, and system ... Student / Intern (Fixed Term) Shift: Shift 1 (United States of America) Primary Location: San Jose ...
New
San Jose, CA ยท On-site
Job Summary As a DFT Intern at Etched, you will help review and refine DFT flow automation to ... Exposure to ASIC or SoC design concepts * Familiarity with digital logic design fundamentals
San Jose, CA ยท On-site
Job Summary As a DFT Intern at Etched, you will help review and refine DFT flow automation to ... Exposure to ASIC or SoC design concepts * Familiarity with digital logic design fundamentals
San Jose, CA ยท On-site
Job Summary As a DFT Intern at Etched, you will help review and refine DFT flow automation to ... Exposure to ASIC or SoC design concepts * Familiarity with digital logic design fundamentals
Quick apply
San Jose, CA ยท On-site
Job Summary As a DFT Intern at Etched, you will help review and refine DFT flow automation to ... Exposure to ASIC or SoC design concepts * Familiarity with digital logic design fundamentals
Austin, TX ยท On-site
$50 - $70/hr
As an intern in the Physical Design (PD) team, you will work on high-performance designs going into ... ASIC. This role is on-site, 40 hours, based out of Santa Clara, CA or Austin, TX. Who You Are
Austin, TX ยท On-site
$50 - $70/hr
As an intern in the Physical Design (PD) team, you will work on high-performance designs going into ... ASIC. This role is on-site, 40 hours, based out of Santa Clara, CA or Austin, TX. Who You Are
Santa Clara, CA ยท Hybrid
$50 - $70/hr
As an intern in the Physical Design (PD) team, you will work on high-performance designs going into ... ASIC. This role is on-site, hybrid, based out of Santa Clara, CA working 4 days in office, 1 day ...
Santa Clara, CA ยท Hybrid
$50 - $70/hr
As an intern in the Physical Design (PD) team, you will work on high-performance designs going into ... ASIC. This role is on-site, hybrid, based out of Santa Clara, CA working 4 days in office, 1 day ...
$50K - $67K/yr
Join Teledyne Imaging Sensors as an RTL Design Engineering Intern Are you ready to launch your ... Exposure to FPGA development or ASIC design flows * Interest in infrared imaging, optics, or sensor ...
$50K - $67K/yr
Join Teledyne Imaging Sensors as an RTL Design Engineering Intern Are you ready to launch your ... Exposure to FPGA development or ASIC design flows * Interest in infrared imaging, optics, or sensor ...
Camarillo, CA ยท On-site
$50K - $67K/yr
Join Teledyne Imaging Sensors as an RTL Design Engineering Intern Are you ready to launch your ... Exposure to FPGA development or ASIC design flows * Interest in infrared imaging, optics, or sensor ...
Camarillo, CA ยท On-site
$50K - $67K/yr
Join Teledyne Imaging Sensors as an RTL Design Engineering Intern Are you ready to launch your ... Exposure to FPGA development or ASIC design flows * Interest in infrared imaging, optics, or sensor ...
Must have experience with digital IC design, methodology, and tools. Should be able to work ... ASIC platforms. Should be able to work with processors, develop algorithms, and optimize ...
Must have experience with digital IC design, methodology, and tools. Should be able to work ... ASIC platforms. Should be able to work with processors, develop algorithms, and optimize ...
Camarillo, CA ยท On-site
$50K - $67K/yr
Join Teledyne Imaging Sensors as an RTL Design Engineering Intern Are you ready to launch your ... Exposure to FPGA development or ASIC design flows * Interest in infrared imaging, optics, or sensor ...
Camarillo, CA ยท On-site
$50K - $67K/yr
Join Teledyne Imaging Sensors as an RTL Design Engineering Intern Are you ready to launch your ... Exposure to FPGA development or ASIC design flows * Interest in infrared imaging, optics, or sensor ...
San Jose, CA ยท On-site
Job Summary As a Physical Design intern for Etched, you will be responsible for realizing our ... Exposure to ASIC or SoC design concepts * Familiarity with SystemVerilog, UVM, or Python
San Jose, CA ยท On-site
Job Summary As a Physical Design intern for Etched, you will be responsible for realizing our ... Exposure to ASIC or SoC design concepts * Familiarity with SystemVerilog, UVM, or Python
Camarillo, CA ยท On-site
$5K/mo
Must have experience with digital IC design, methodology, and tools. Should be able to work ... ASIC platforms. Should be able to work with processors, develop algorithms, and optimize ...
Camarillo, CA ยท On-site
$5K/mo
Must have experience with digital IC design, methodology, and tools. Should be able to work ... ASIC platforms. Should be able to work with processors, develop algorithms, and optimize ...
San Jose, CA ยท On-site
Job Summary As a Physical Design intern for Etched, you will be responsible for realizing our ... Exposure to ASIC or SoC design concepts * Familiarity with SystemVerilog, UVM, or Python
Quick apply
San Jose, CA ยท On-site
Job Summary As a Physical Design intern for Etched, you will be responsible for realizing our ... Exposure to ASIC or SoC design concepts * Familiarity with SystemVerilog, UVM, or Python
$9.13 - $11.65
9% of jobs
$11.65 - $14.16
8% of jobs
$14.81 is the 25th percentile. Wages below this are outliers.
$14.16 - $16.67
28% of jobs
The median wage is $17.34 / hr.
$16.67 - $19.19
16% of jobs
$20.91 is the 75th percentile. Wages above this are outliers.
$19.19 - $21.70
20% of jobs
$21.70 - $24.21
9% of jobs
$24.21 - $26.73
4% of jobs
$26.73 - $29.24
1% of jobs
$29.24 - $31.75
1% of jobs
$31.75 - $34.27
1% of jobs
$34.27 - $36.78
2% of jobs
$9
$19
$36
An ASIC Design Intern assists in the design, verification, and testing of Application-Specific Integrated Circuits (ASICs). Interns work with experienced engineers to develop digital or analog circuit designs, run simulations, and debug hardware issues. They gain hands-on experience with design tools, scripting languages, and verification methodologies. This role provides valuable industry exposure and helps interns build skills in VLSI, RTL design, and semiconductor development.
To thrive as an ASIC Design Intern, you need a solid foundation in digital logic design, computer architecture, and proficiency with hardware description languages such as Verilog or VHDL, typically supported by coursework in electrical or computer engineering. Familiarity with industry-standard EDA tools like Cadence or Synopsys and experience with simulation and debugging environments are highly valued. Strong problem-solving skills, attention to detail, and effective communication make you stand out in collaborative team projects. These skills ensure you can contribute effectively to complex design tasks, learn quickly, and integrate seamlessly into professional ASIC development teams.
As an ASIC Design Intern, your responsibilities may include assisting with the design and verification of digital circuits, creating testbenches, running simulations, and helping debug hardware issues alongside experienced engineers. You may also document design processes, participate in reviews, and contribute to tool flow development or optimization tasks. Interns often work closely with senior design, verification, and physical design engineers, gaining exposure to a variety of stages in the ASIC development lifecycle. This hands-on experience not only builds your technical expertise but also helps you develop teamwork and project management skills, which are essential for advancing in hardware engineering roles.

Full-time
Posted 6 days ago