Develop and improve workflows throughout the FPGA / HDL design cycle (Architecture, functional block definition, simulation, system testing, HDL library standardization). * Collaborate with internal ...
Develop and improve workflows throughout the FPGA / HDL design cycle (Architecture, functional block definition, simulation, system testing, HDL library standardization). * Collaborate with internal ...
Develop and improve workflows throughout the FPGA / HDL design cycle (Architecture, functional block definition, simulation, system testing, HDL library standardization) * Collaborate with internal ...
Develop and improve workflows throughout the FPGA / HDL design cycle (Architecture, functional block definition, simulation, system testing, HDL library standardization) * Collaborate with internal ...
Design Engineer
San Jose, CA · On-site
Implement design modules using hardware description language (HDL). * Design schemes for multi-clock domain crossing and synchronization. * Drive OVM/UVM design verification and support FPGA ...
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Design Engineer
San Jose, CA · On-site
Implement design modules using hardware description language (HDL). * Design schemes for multi-clock domain crossing and synchronization. * Drive OVM/UVM design verification and support FPGA ...
Develop and improve workflows throughout the FPGA / HDL design cycle (Architecture, functional block definition, simulation, system testing, HDL library standardization). * Collaborate with internal ...
Develop and improve workflows throughout the FPGA / HDL design cycle (Architecture, functional block definition, simulation, system testing, HDL library standardization). * Collaborate with internal ...
Performs design/HDL analysis, including high speed and low power designs. Participates in simulation, verification, and integration tasks. Takes algorithmic or functional specifications and coverts ...
Performs design/HDL analysis, including high speed and low power designs. Participates in simulation, verification, and integration tasks. Takes algorithmic or functional specifications and coverts ...
Principal Digital Hardware Engineer (PCBs/FPGAs/HDL)
Costa Mesa, CA · On-site
$220K - $292K/yr
Develop and improve workflows throughout the FPGA / HDL design cycle (Architecture, functional block definition, simulation, system testing, HDL library standardization). * Collaborate with internal ...
Principal Digital Hardware Engineer (PCBs/FPGAs/HDL)
Costa Mesa, CA · On-site
$220K - $292K/yr
Develop and improve workflows throughout the FPGA / HDL design cycle (Architecture, functional block definition, simulation, system testing, HDL library standardization). * Collaborate with internal ...
Principal Digital Hardware Engineer (PCBs/FPGAs/HDL)
Costa Mesa, CA · On-site
$220K - $292K/yr
Develop and improve workflows throughout the FPGA / HDL design cycle (Architecture, functional block definition, simulation, system testing, HDL library standardization). * Collaborate with internal ...
Principal Digital Hardware Engineer (PCBs/FPGAs/HDL)
Costa Mesa, CA · On-site
$220K - $292K/yr
Develop and improve workflows throughout the FPGA / HDL design cycle (Architecture, functional block definition, simulation, system testing, HDL library standardization). * Collaborate with internal ...
Develop and improve workflows throughout the FPGA / HDL design cycle (Architecture, functional block definition, simulation, system testing, HDL library standardization). * Collaborate with internal ...
Develop and improve workflows throughout the FPGA / HDL design cycle (Architecture, functional block definition, simulation, system testing, HDL library standardization). * Collaborate with internal ...
Develop and improve workflows throughout the FPGA / HDL design cycle (Architecture, functional block definition, simulation, system testing, HDL library standardization) * Collaborate with internal ...
Develop and improve workflows throughout the FPGA / HDL design cycle (Architecture, functional block definition, simulation, system testing, HDL library standardization) * Collaborate with internal ...
Develop and improve workflows throughout the FPGA / HDL design cycle (Architecture, functional block definition, simulation, system testing, HDL library standardization) * Collaborate with internal ...
Develop and improve workflows throughout the FPGA / HDL design cycle (Architecture, functional block definition, simulation, system testing, HDL library standardization) * Collaborate with internal ...
Senior Manager - Electrical Engineering, Compute HW & HDL
Costa Mesa, CA · On-site
$170K - $255K/yr
Develop and improve workflows throughout the FPGA / HDL design cycle (Architecture, functional block definition, simulation, system testing, HDL library standardization) * Collaborate with internal ...
Senior Manager - Electrical Engineering, Compute HW & HDL
Costa Mesa, CA · On-site
$170K - $255K/yr
Develop and improve workflows throughout the FPGA / HDL design cycle (Architecture, functional block definition, simulation, system testing, HDL library standardization) * Collaborate with internal ...
Principal FPGA/ASIC Engineer - Level 3
Gilbert, AZ · On-site
$79K - $118K/yr
HDL design for FPGA and/or ASIC applications * FPGA/ASIC verification via simulation and emulation (lab testing) * FPGA/ASIC synthesis, timing analysis, and place & route * FPGA design for space ...
Principal FPGA/ASIC Engineer - Level 3
Gilbert, AZ · On-site
$79K - $118K/yr
HDL design for FPGA and/or ASIC applications * FPGA/ASIC verification via simulation and emulation (lab testing) * FPGA/ASIC synthesis, timing analysis, and place & route * FPGA design for space ...
Develop and improve workflows throughout the FPGA / HDL design cycle (Architecture, functional block definition, simulation, system testing, HDL library standardization) * Collaborate with internal ...
Develop and improve workflows throughout the FPGA / HDL design cycle (Architecture, functional block definition, simulation, system testing, HDL library standardization) * Collaborate with internal ...
R&D Gateware (FPGA) Design, BS/MS EE or CE
Budd Lake, NJ · On-site
$138K - $231K/yr
Skills in HDL programming targeting Xilinx and Intel/Altera devices, discrete time systems theory, digital design, DSP, and control systems theory are ideal. Exposure to power electronics is highly ...
R&D Gateware (FPGA) Design, BS/MS EE or CE
Budd Lake, NJ · On-site
$138K - $231K/yr
Skills in HDL programming targeting Xilinx and Intel/Altera devices, discrete time systems theory, digital design, DSP, and control systems theory are ideal. Exposure to power electronics is highly ...
Senior FPGA Engineer, EW
$139K - $179K/yr
Design custom, and optimized, HDL for software defined radios. * Develop drivers for custom RF component boards (PLLs, mixed signal front ends, etc) REQUIRED QUALIFICATIONS * Strong experience with ...
Senior FPGA Engineer, EW
$139K - $179K/yr
Design custom, and optimized, HDL for software defined radios. * Develop drivers for custom RF component boards (PLLs, mixed signal front ends, etc) REQUIRED QUALIFICATIONS * Strong experience with ...
R&D Gateware (FPGA) Design, BS/MS EE or CE
$138K - $231K/yr
Skills in HDL programming targeting Xilinx and Intel/Altera devices, discrete time systems theory, digital design, DSP, and control systems theory are ideal. Exposure to power electronics is highly ...
R&D Gateware (FPGA) Design, BS/MS EE or CE
$138K - $231K/yr
Skills in HDL programming targeting Xilinx and Intel/Altera devices, discrete time systems theory, digital design, DSP, and control systems theory are ideal. Exposure to power electronics is highly ...
HDL Technical Team Lead
Boulder, CO · On-site
Lead technical planning, design reviews, and cross-team alignment -- ensuring teams move quickly without sacrificing quality * Spend ~50% of your time on specialty tooling, targeted HDL development ...
HDL Technical Team Lead
Boulder, CO · On-site
Lead technical planning, design reviews, and cross-team alignment -- ensuring teams move quickly without sacrificing quality * Spend ~50% of your time on specialty tooling, targeted HDL development ...
FPGA/RTL Design Engineer - III (W2 Only)
$134K - $184K/yr
Previous design experience with ARM based SoC, including AXI/ACE and APB bus protocols Experience in HDL design with Verilog/SystemVerilog Experience with ASIC and/or SoC design flows and methodology ...
FPGA/RTL Design Engineer - III (W2 Only)
$134K - $184K/yr
Previous design experience with ARM based SoC, including AXI/ACE and APB bus protocols Experience in HDL design with Verilog/SystemVerilog Experience with ASIC and/or SoC design flows and methodology ...
Positions Available - Senior Electrical Design Engineer (Digital Circuit Design)- Salt Lake City, UT
Elkhart, IN · On-site
$99K - $134K/yr
Experience with FPGA/HDL design (Verilog or VHDL) * Exposure to manufacturing processes and DFM/DFA principles * Strong attention to detail and design accuracy * Ability to manage multiple projects ...
Positions Available - Senior Electrical Design Engineer (Digital Circuit Design)- Salt Lake City, UT
Elkhart, IN · On-site
$99K - $134K/yr
Experience with FPGA/HDL design (Verilog or VHDL) * Exposure to manufacturing processes and DFM/DFA principles * Strong attention to detail and design accuracy * Ability to manage multiple projects ...
HDL Technical Team Lead
Boulder, CO · On-site
$150K - $250K/yr
Lead technical planning, design reviews, and cross-team alignment - ensuring teams move quickly without sacrificing quality * Spend ~50% of your time on specialty tooling, targeted HDL development ...
HDL Technical Team Lead
Boulder, CO · On-site
$150K - $250K/yr
Lead technical planning, design reviews, and cross-team alignment - ensuring teams move quickly without sacrificing quality * Spend ~50% of your time on specialty tooling, targeted HDL development ...
Hdl Design information
See salary details
$5.29 - $8.92
0% of jobs
$8.92 - $12.54
0% of jobs
$12.54 - $16.17
0% of jobs
$16.17 - $19.80
0% of jobs
$19.80 - $23.43
0% of jobs
$23.43 - $27.05
0% of jobs
$27.05 - $30.68
0% of jobs
$30.68 - $34.31
0% of jobs
$34.31 - $37.94
0% of jobs
$37.94 - $41.56
0% of jobs
$42.47 is the 25th percentile. Wages below this are outliers.
$41.56 - $45.19
100% of jobs
$5
$45
How much do hdl design jobs pay per hour?
What are some common challenges faced by HDL Design engineers when working on large-scale projects?
What are the key skills and qualifications needed to thrive as an HDL Designer, and why are they important?
What is HDL design?
What is the difference between Hdl Design vs Digital Design?
| Aspect | Hdl Design | Digital Design |
|---|---|---|
| Primary Focus | Creating hardware description language code for digital circuits | Designing digital system architectures and logic |
| Skills Required | VHDL/Verilog, hardware concepts, simulation tools | VHDL/Verilog, digital logic, system architecture |
| Work Environment | Hardware development labs, FPGA/ASIC design teams | Electronics and embedded systems teams, design studios |
Hdl Design primarily involves writing code in hardware description languages like VHDL or Verilog to develop digital hardware components. Digital Design encompasses a broader scope, including system-level architecture and logic design, often using similar languages. While both roles require knowledge of digital logic and HDL skills, Hdl Design is more focused on coding and simulation, whereas Digital Design emphasizes system integration and architecture planning.

Other
Posted 6 days ago
Anduril rating
9.4
Based on 7 frontline employees who took The Breakroom Quiz
Job description
- Technical lead for electrical engineering team, creating embedded compute solutions for vehicle management, DSP, and networking.
- Own the full PCB development cycle of host boards for FPGAs / SoCs / SoMs (Developing requirements, schematic capture, board layout, bring-up, test, and integration).
- Develop and improve workflows throughout the FPGA / HDL design cycle (Architecture, functional block definition, simulation, system testing, HDL library standardization).
- Collaborate with internal stakeholders to develop a strategy for developing and rolling out your compute solutions across Anduril in a scalable manner.
- Create, maintain and communicate product development schedules with sufficient detail to ensure that all assigned personnel are aware of their tasks and deadlines.
- Bachelor's Degree in Electrical Engineering or equivalent
- 15+ years of experience designing, testing and troubleshooting complex board designs in military, automotive or similar hardware.
- Experience with leading an Electrical Engineering team focused on Digital Design
- Proficiency in an HDL language (VHDL, Verilog)
- Familiarity with common MCU, CPU, FPGA devices and technologies.
- Familiarity with standard interfaces such as Ethernet, CAN, I2C, SPI, PCIe, USB, etc.
- Experience in design for signal integrity / power integrity.
- Knowledge of modern analog and digital electronics and electronic circuits.
- Competence with test equipment such as oscilloscopes, logic analyzers, thermal chambers, current-probes, and automation of tests.
- Proficient with Altium Designer or equivalent electronic design automation design tool
- Eligible to obtain and maintain an active U.S. Top Secret security clearance
- Understanding and familiarity with DO-254, DO-178C, DO-160, DO-311A
- Understanding and familiarity with MIL-STD-810, MIL-STD-704, MIL-STD-461
- Expertise in computer networking
- Experience with implementing enhanced security measures
About Anduril Industries
Sourced by ZipRecruiter
Anduril Industries is a trailblazer in the technology industry based in Costa Mesa, CA, US. Founded in 2017 by Palmer Luckey, the creator of Oculus VR, the company focuses on developing innovative technology to equip and empower those in the defense sector. Its primary products include cutting-edge autonomous systems and AI software that assist in combating threats to national and global security. The mission of Anduril Industries is to integrate technology and defense by building transformative, scalable solutions that ensure a safer world.
Industry
Guided missile and space vehicle manufacturing
Company size
501 - 1,000 Employees
Headquarters location
Costa Mesa, CA, US
Year founded
2017