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Asic Design Intern Jobs (NOW HIRING)

Etched

RTL Intern

San Jose, CA · On-site

Job Summary As an RTL Intern at Etched, you will help design microarchitecture and implement logic ... Exposure to ASIC or SoC design concepts * Familiarity with SystemVerilog, UVM, or Python

Etched

DV Intern

San Jose, CA · On-site

Job Summary As a Design Verification intern, you will ensure the custom IPs powering our chips ... Exposure to ASIC or SoC design concepts * Familiarity with SystemVerilog, UVM, or Python

Etched

DV Intern

San Jose, CA · On-site

Job Summary As aDesign Verification intern, you will ensure the custom IPs powering our chips ... Exposure to ASIC or SoC design concepts * Familiarity with SystemVerilog, UVM, or Python

Jane Street

Hardware Engineer (FPGA/ASIC)

New York, NY · On-site

... design it. Some intern projects consider big-picture questions that we're still trying to figure ... Experienced working with FPGA or ASIC vendor tools - Vivado or Quartus for FPGAs, Genus or Innovus ...

Etched

Electrical Platform Intern

San Jose, CA · On-site

$22.25 - $29.25/hr

We are seeking interns to work across all aspects of mechanical and electrical engineering to design the future of high power ASIC systems. We are looking for Fall '26, Spring '27, and Summer '27 ...

Etched

Electrical Platform Intern

San Jose, CA · On-site

$22.25 - $29.25/hr

We are seeking interns to work across all aspects of mechanical and electrical engineering to design the future of high power ASIC systems. We are looking for Fall '26, Spring '27, and Summer '27 ...

Etched

Mech / Thermal Intern

San Jose, CA · On-site

$22 - $29.50/hr

We are seeking interns to work across all aspects of mechanical and electrical engineering to design the future of high power ASIC systems. We are looking for Summer '26, Fall '26, Spring '27, and ...

Etched

Mech / Thermal Intern

San Jose, CA · On-site

$22 - $29.50/hr

We are seeking interns to work across all aspects of mechanical and electrical engineering to design the future of high power ASIC systems. We are looking for Summer '26, Fall '26, Spring '27, and ...

Etched

Infrastructure Intern

San Jose, CA · On-site

We co-design chips, racks, software, and manufacturing to deliver best-in-class throughput and ... ASIC, Software, and Platform engineers to iterate faster, build more reliably, and push the ...

Etched

Infrastructure Intern

San Jose, CA · On-site

We co-design chips, racks, software, and manufacturing to deliver best-in-class throughput and ... ASIC, Software, and Platform engineers to iterate faster, build more reliably, and push the ...

INVENSENSE

Product - Sr Staff

San Jose, CA · On-site

$140K - $180K/yr

We're looking for top-notch students to join our global intern team. If you're interested in being ... Responsibilities • Drives technical collaboration between internal teams and owns the design ...

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Asic Design Intern information

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How much do asic design intern jobs pay per hour?

As of Jul 18, 2026, the average hourly pay for asic design intern in the United States is $19.38, according to ZipRecruiter salary data. Most workers in this role earn between $14.42 and $21.63 per hour, depending on experience, location, and employer.

What is an ASIC Design Intern job?

An ASIC Design Intern assists in the design, verification, and testing of Application-Specific Integrated Circuits (ASICs). Interns work with experienced engineers to develop digital or analog circuit designs, run simulations, and debug hardware issues. They gain hands-on experience with design tools, scripting languages, and verification methodologies. This role provides valuable industry exposure and helps interns build skills in VLSI, RTL design, and semiconductor development.

What are the key skills and qualifications needed to thrive in the Asic Design Intern position, and why are they important?

To thrive as an ASIC Design Intern, you need a solid foundation in digital logic design, computer architecture, and proficiency with hardware description languages such as Verilog or VHDL, typically supported by coursework in electrical or computer engineering. Familiarity with industry-standard EDA tools like Cadence or Synopsys and experience with simulation and debugging environments are highly valued. Strong problem-solving skills, attention to detail, and effective communication make you stand out in collaborative team projects. These skills ensure you can contribute effectively to complex design tasks, learn quickly, and integrate seamlessly into professional ASIC development teams.

What are the typical responsibilities of an ASIC Design Intern during their internship?

As an ASIC Design Intern, your responsibilities may include assisting with the design and verification of digital circuits, creating testbenches, running simulations, and helping debug hardware issues alongside experienced engineers. You may also document design processes, participate in reviews, and contribute to tool flow development or optimization tasks. Interns often work closely with senior design, verification, and physical design engineers, gaining exposure to a variety of stages in the ASIC development lifecycle. This hands-on experience not only builds your technical expertise but also helps you develop teamwork and project management skills, which are essential for advancing in hardware engineering roles.

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Asic Design Intern jobs near you
Infographic showing various Asic Design Intern job openings in the United States as of July 2026, with employment types broken down into 95% Full Time, 1% Part Time, 2% Contract, and 2% Summer. Highlights an 89% Physical, 6% Hybrid, and 5% Remote job distribution, with an average salary of $40,304 per year, or $19.4 per hour.

RTL Intern

Etched

San Jose, CA • On-site

Other

Re-posted 11 days ago

Job description

About Etched

Etched is building hardware for frontier intelligence. We co-design chips, racks, software, and manufacturing to deliver best-in-class throughput and latency across both prefill and decode workloads. Our first products are heavily focused on inference. Backed by hundreds of millions from top-tier investors and staffed by leading engineers, Etched is redefining the infrastructure layer for the fastest growing industry in history.

Job Summary

As an RTL Intern at Etched, you will help design microarchitecture and implement logic in verilog. You will work with cutting-edge machine learning architectures, contribute to RTL block development, and participate in the full design cycle—from microarchitecture discussions to synthesis and timing feedback. You do not necessarily need prior ML/AI hardware experience; just the ability to learn quickly in a fast-paced, high-autonomy environment. We are looking for Fall '26, Spring '27, and Summer '27 interns.

You may be a good fit if you have

  • Progress towards a Bachelor’s, Master’s, or PhD degree in electrical engineering, computer engineering, or a related field.

  • Familiarity with high-speed digital logic

  • Exposure to ASIC or SoC design concepts

  • Familiarity with SystemVerilog, UVM, or Python

  • Familiarity with verification work and writing test benches

  • Familiarity with physical design flows and tooling

  • Are able to learn quickly about transformers and other aspects of modern artificial intelligence

Strong candidates may also have experience with

  • Familiarity with modern ML and LLM model architectures

  • Familiarity with numerical representations and functions

  • Familiarity with clocking and reset schemes

  • ​Ability to program with Python or another scripting language

We encourage you to apply even if you do not believe you meet every single qualification.

Program details

  • 12-week paid internship

  • Generous housing support for those relocating

  • Daily lunch and dinner in our office

  • Based at our office in San Jose, CA

  • Direct mentorship from industry leaders and world-class engineers

  • Opportunity to work on one of the most important problems of our time

For any questions, contact internships@etched.com

How we’re different

Etched believes in the Bitter Lesson. We are the first inference-focused frontier AI system, betting early on transformer and transformer-like architectures and on increasing model sizes. Our addressable market is the entirety of inference, unlike many of our competitors.

We are a fully in-person team in San Jose (Santana Row), and greatly value engineering skills. We do not have boundaries between engineering and research, and we expect all of our technical staff to contribute to both and work across disciplines as needed.