Minimum Qualifications 10 + years of full time ASIC design experience memory system development RTL/micro-architecture definition PPA (performance/power/area) analysis Cache design background ...
Minimum Qualifications 10 + years of full time ASIC design experience memory system development RTL/micro-architecture definition PPA (performance/power/area) analysis Cache design background ...
Minimum Qualifications 3+ years of full time ASIC design experience memory system development RTL/micro-architecture definition PPA (performance/power/area) analysis B.S. in a relevant field ...
Minimum Qualifications 3+ years of full time ASIC design experience memory system development RTL/micro-architecture definition PPA (performance/power/area) analysis B.S. in a relevant field ...
ASIC Design Engineer - Cache Controller
$147K - $272K/yr
Minimum Qualifications 3+ years of full time ASIC design experience memory system development RTL/micro-architecture definition PPA (performance/power/area) analysis B.S. in a relevant field Pay ...
ASIC Design Engineer - Cache Controller
$147K - $272K/yr
Minimum Qualifications 3+ years of full time ASIC design experience memory system development RTL/micro-architecture definition PPA (performance/power/area) analysis B.S. in a relevant field Pay ...
ASIC Design Engineer - Cache Controller
$181K - $318K/yr
Minimum Qualifications 10 + years of full time ASIC design experience memory system development RTL/micro-architecture definition PPA (performance/power/area) analysis Cache design background ...
ASIC Design Engineer - Cache Controller
$181K - $318K/yr
Minimum Qualifications 10 + years of full time ASIC design experience memory system development RTL/micro-architecture definition PPA (performance/power/area) analysis Cache design background ...
General Summary This full-time position is in the Systems Development Department of Kratos SRE and ... of ASIC development * 2+ years of design implementation and verification using Verilog/VHDL * 5+ ...
General Summary This full-time position is in the Systems Development Department of Kratos SRE and ... of ASIC development * 2+ years of design implementation and verification using Verilog/VHDL * 5+ ...
PCIe ASIC Design Engineer
Austin, TX · On-site +1
We're seeking engineers who are energized by working on cutting-edge ASIC design and distributed ... full-time exempt employees. Other paid time off benefits include sick time, bonding leave, and ...
PCIe ASIC Design Engineer
Austin, TX · On-site +1
We're seeking engineers who are energized by working on cutting-edge ASIC design and distributed ... full-time exempt employees. Other paid time off benefits include sick time, bonding leave, and ...
ASIC Design Verification Lead
Austin, TX · On-site +1
We're seeking engineers who are energized by working on cutting-edge ASIC design and distributed ... full-time exempt employees. Other paid time off benefits include sick time, bonding leave, and ...
ASIC Design Verification Lead
Austin, TX · On-site +1
We're seeking engineers who are energized by working on cutting-edge ASIC design and distributed ... full-time exempt employees. Other paid time off benefits include sick time, bonding leave, and ...
ASIC Design Verification Lead
Austin, TX · On-site
We're seeking engineers who are energized by working on cutting-edge ASIC design and distributed ... full-time exempt employees. Other paid time off benefits include sick time, bonding leave, and ...
ASIC Design Verification Lead
Austin, TX · On-site
We're seeking engineers who are energized by working on cutting-edge ASIC design and distributed ... full-time exempt employees. Other paid time off benefits include sick time, bonding leave, and ...
PCIe ASIC Design Engineer
Austin, TX · On-site
We're seeking engineers who are energized by working on cutting-edge ASIC design and distributed ... full-time exempt employees. Other paid time off benefits include sick time, bonding leave, and ...
PCIe ASIC Design Engineer
Austin, TX · On-site
We're seeking engineers who are energized by working on cutting-edge ASIC design and distributed ... full-time exempt employees. Other paid time off benefits include sick time, bonding leave, and ...
Asic Design Engineer Location: Mountain View CA (Remote) Note: Seeking candidate with Fusion ... US-CA-Mountain View, California (Google) Time Type: Full time Job Category: Engineering Services ...
Asic Design Engineer Location: Mountain View CA (Remote) Note: Seeking candidate with Fusion ... US-CA-Mountain View, California (Google) Time Type: Full time Job Category: Engineering Services ...
Senior ASIC Design Engineer
Dallas, TX · On-site +1
We're seeking engineers who are energized by working on cutting-edge ASIC design and distributed ... full-time exempt employees. Other paid time off benefits include sick time, bonding leave, and ...
Senior ASIC Design Engineer
Dallas, TX · On-site +1
We're seeking engineers who are energized by working on cutting-edge ASIC design and distributed ... full-time exempt employees. Other paid time off benefits include sick time, bonding leave, and ...
ASIC Verification Engineer (Remote)
Williston, VT · On-site +1
$120K - $165K/yr
We are presently seeking an experienced Full-Time ASIC Verification Engineer to help accelerate the ... microprocessor design, computer architecture, VLSI design, software/programming courses)
ASIC Verification Engineer (Remote)
Williston, VT · On-site +1
$120K - $165K/yr
We are presently seeking an experienced Full-Time ASIC Verification Engineer to help accelerate the ... microprocessor design, computer architecture, VLSI design, software/programming courses)
Were seeking engineers who are energized by working on cutting-edge ASIC design and distributed ... full-time exempt employees. Other paid time off benefits include sick time, bonding leave, and ...
Quick apply
Were seeking engineers who are energized by working on cutting-edge ASIC design and distributed ... full-time exempt employees. Other paid time off benefits include sick time, bonding leave, and ...
Senior ASIC Design Engineer
Dallas, TX · On-site
We're seeking engineers who are energized by working on cutting-edge ASIC design and distributed ... full-time exempt employees. Other paid time off benefits include sick time, bonding leave, and ...
Senior ASIC Design Engineer
Dallas, TX · On-site
We're seeking engineers who are energized by working on cutting-edge ASIC design and distributed ... full-time exempt employees. Other paid time off benefits include sick time, bonding leave, and ...
ASIC Design Engineer Technical Lead
San Jose, CA · On-site
$183K - $263K/yr
Bachelor's degree in Electrical or Computer engineering and 10+ years of ASIC Design experience or ... for full-time employees * Exempt employees participate in Cisco's flexible vacation time off ...
ASIC Design Engineer Technical Lead
San Jose, CA · On-site
$183K - $263K/yr
Bachelor's degree in Electrical or Computer engineering and 10+ years of ASIC Design experience or ... for full-time employees * Exempt employees participate in Cisco's flexible vacation time off ...
ASIC Design Engineer Technical Lead
San Jose, CA · On-site
$183K - $263K/yr
Bachelor's degree in Electrical or Computer engineering and 10+ years of ASIC Design experience or ... for full-time employees * Exempt employees participate in Cisco's flexible vacation time off ...
ASIC Design Engineer Technical Lead
San Jose, CA · On-site
$183K - $263K/yr
Bachelor's degree in Electrical or Computer engineering and 10+ years of ASIC Design experience or ... for full-time employees * Exempt employees participate in Cisco's flexible vacation time off ...
ASIC Design Verification Engineer
San Jose, CA · On-site
$152K - $219K/yr
What You'll Do As an ASIC Design Verification Engineer, you will play a critical role in developing ... for full-time employees * Exempt employees participate in Cisco's flexible vacation time off ...
ASIC Design Verification Engineer
San Jose, CA · On-site
$152K - $219K/yr
What You'll Do As an ASIC Design Verification Engineer, you will play a critical role in developing ... for full-time employees * Exempt employees participate in Cisco's flexible vacation time off ...
Front-End ASIC Design Engineer - [FullTime] (IK)
Milpitas, CA · On-site
$175K - $200K/yr
... design. • Hands-on ASIC front-end design, ideally in design services environments (product ... No Compensation Base Salary - USD $175,000 to $200,000 Full-time Benefits - Full Required: 10+ to ...
Front-End ASIC Design Engineer - [FullTime] (IK)
Milpitas, CA · On-site
$175K - $200K/yr
... design. • Hands-on ASIC front-end design, ideally in design services environments (product ... No Compensation Base Salary - USD $175,000 to $200,000 Full-time Benefits - Full Required: 10+ to ...
ASIC Design Verification Engineer
San Jose, CA · On-site
$152K - $219K/yr
What You'll Do As an ASIC Design Verification Engineer, you will play a critical role in developing ... for full-time employees * Exempt employees participate in Cisco's flexible vacation time off ...
ASIC Design Verification Engineer
San Jose, CA · On-site
$152K - $219K/yr
What You'll Do As an ASIC Design Verification Engineer, you will play a critical role in developing ... for full-time employees * Exempt employees participate in Cisco's flexible vacation time off ...
ASIC Design Verification Engineer
San Jose, CA · On-site
$165K - $241K/yr
Participate in the ASIC design verification for Cisco high-end switching products. * Perform end-to ... for full-time employees * Exempt employees participate in Cisco's flexible vacation time off ...
ASIC Design Verification Engineer
San Jose, CA · On-site
$165K - $241K/yr
Participate in the ASIC design verification for Cisco high-end switching products. * Perform end-to ... for full-time employees * Exempt employees participate in Cisco's flexible vacation time off ...
Full Time Asic Design information
See salary details
$94K - $103.8K
16% of jobs
$103.8K - $113.6K
3% of jobs
$113.6K - $123.5K
4% of jobs
$126.3K is the 25th percentile. Wages below this are outliers.
$123.5K - $133.3K
6% of jobs
The median wage is $139.4K / yr.
$133.3K - $143.1K
33% of jobs
$143.1K - $152.9K
3% of jobs
$152.9K - $162.7K
2% of jobs
$169.2K is the 75th percentile. Wages above this are outliers.
$162.7K - $172.5K
12% of jobs
$172.5K - $182.4K
5% of jobs
$182.4K - $192.2K
4% of jobs
$192.2K - $202K
12% of jobs
$94K
$150.2K
$202K
How much do full time asic design jobs pay per year?
What are the key skills and qualifications needed to thrive as a Full Time ASIC Design Engineer, and why are they important?
What are Full Time ASIC Design jobs?
What are some common challenges faced by ASIC Design Engineers in a full-time role, and how can they be addressed?
What is the difference between Full Time Asic Design vs Full Time FPGA Design?
| Aspect | Full Time Asic Design | Full Time FPGA Design |
|---|---|---|
| Credentials | Bachelor's or Master's in Electrical Engineering or Computer Engineering | Bachelor's or Master's in Electrical Engineering or Computer Engineering |
| Work Environment | Designing custom silicon chips for manufacturing | Developing programmable logic devices for prototyping and applications |
| Industry Usage | Semiconductor companies, chip manufacturers | |
| Work Focus | Creating permanent, optimized chip designs | Implementing flexible, reconfigurable logic solutions |
Full Time Asic Design and Full Time FPGA Design roles share similar educational backgrounds and industry environments. However, Asic Design focuses on creating permanent, optimized chips for mass production, while FPGA Design involves developing reconfigurable logic devices for testing and specific applications. Both roles are essential in the semiconductor industry but serve different purposes in hardware development.
Apple rating
8.1
Based on 666 frontline employees who took The Breakroom Quiz
6th of 30 rated technology retailers
Job description
Description
Design and develop hardware for cache subsystem in high performance system on a chip (SoC).
Develop cache micro-architecture based on architecture guidelines and model analysis.
Explore architecture trade-offs in system performance, area, and power consumption.
Develop and debug register-transfer level (RTL) design of various sections in the cache subsystem.
Work on front-end netlist and area/timing analysis of the cache subsystem.
Work with physical design team on the timing closure of the cache subsystem.
Minimum Qualifications
10 + years of full time ASIC design experience
memory system development
RTL/micro-architecture definition
PPA (performance/power/area) analysis
Cache design background including an understanding of different memory organizations and tradeoffs.
Hands on Experience with multi-processor cache coherence protocols
B.S. in a relevant field
Preferred Qualifications
Knowledge of high-performance coherent memory systems or interconnect architectures
Knowledge of high-performance DRAM controller
M.S in a relevant field.
About Apple
Sourced by ZipRecruiter
Imagine what you could do here! At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, intelligent people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same real passion for innovation that goes into our products also applies to our practices strengthening our dedication to leave the world better than we found it.
Industry
Computer and electronic product manufacturing
Company size
10,000+ Employees
Headquarters location
Cupertino, CA, US
Year founded
1976