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Full Time Asic Design Jobs (NOW HIRING)

We're seeking engineers who are energized by working on cutting-edge ASIC design and distributed ... full-time exempt employees. Other paid time off benefits include sick time, bonding leave, and ...

Job #215247 Chipton-Ross is seeking an FPGA/ASIC Design Engineer for a contract opportunity in ... WORK HOURS Full-Time Monday-Friday 08:00am-05:00pm ADDITIONAL Active secret clearance required.

ASIC Design Verification Engineer

San Jose, CA ยท On-site

$165K - $241K/yr

Participate in the ASIC design verification for Cisco high-end switching products. * Perform end-to ... for full-time employees * Exempt employees participate in Cisco's flexible vacation time off ...

Participate in the ASIC design verification for Cisco high-end switching products. * Perform end-to ... for full-time employees * Exempt employees participate in Cisco's flexible vacation time off ...

Participate in the ASIC design verification for Cisco high-end switching products. * Architect ... for full-time employees * Exempt employees participate in Cisco's flexible vacation time off ...

Participate in the ASIC design verification for Cisco high-end switching products. * Architect ... for full-time employees * Exempt employees participate in Cisco's flexible vacation time off ...

Sr. ASIC Design Engineer

San Jose, CA ยท On-site

$168K - $336K/yr

As a Senior ASIC Design Engineer and domain expert, you will perform logic design across the full ... full-time position is: $168,000.00 - $336,000.00 a year Additional compensation may include ...

As a Senior ASIC Design Engineer and domain expert, you will perform logic design across the full ... full-time position is: $168,000.00 - $336,000.00 a year Additional compensation may include ...

Showing results 21-40

Full Time Asic Design information

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$94K

$150.2K

$202K

How much do full time asic design jobs pay per year?

As of Aug 8, 2026, the average yearly pay for full time asic design in the United States is $150,195.00, according to ZipRecruiter salary data. Most workers in this role earn between $131,500.00 and $180,000.00 per year, depending on experience, location, and employer.

What are the key skills and qualifications needed to thrive as a full time ASIC design engineer?

To thrive as a Full Time ASIC Design Engineer, you need a strong background in electrical engineering, digital logic design, and experience with hardware description languages like Verilog or VHDL, typically backed by a relevant degree. Familiarity with EDA tools such as Synopsys, Cadence, and simulation environments, as well as knowledge of industry standards like IEEE, is crucial. Strong analytical skills, attention to detail, and effective communication are important soft skills that help in collaborating with cross-functional teams and solving complex design challenges. These skills ensure the successful creation, verification, and implementation of high-performance, reliable ASICs in demanding technology environments.

What is a full time ASIC design job?

Full Time ASIC Design jobs involve working as an engineer to create Application-Specific Integrated Circuits (ASICs), which are custom-designed chips for specific applications. These roles typically require expertise in digital or analog circuit design, verification, and often involve using hardware description languages like Verilog or VHDL. Full-time positions mean working standard hours as a permanent employee, often collaborating with teams to take designs from the concept stage through to silicon manufacturing and testing. ASIC designers are crucial in industries like consumer electronics, automotive, telecommunications, and more, where specialized hardware is needed.

What are some common challenges faced by ASIC design engineers in a full-time role, and how can they be addressed?

Full-time ASIC Design Engineers often encounter challenges such as meeting tight project deadlines, managing complex design specifications, and ensuring the design meets both performance and power requirements. Navigating evolving technology nodes and collaborating effectively with cross-functional teams, such as verification and layout engineers, can also be demanding. These challenges can be addressed by maintaining clear communication with team members, staying up-to-date with industry tools and methodologies, and adopting robust design and verification processes. Being proactive about troubleshooting and continuous learning helps make the role both manageable and rewarding.

What is the difference between Full Time Asic Design vs Full Time FPGA Design?

AspectFull Time Asic DesignFull Time FPGA Design
CredentialsBachelor's or Master's in Electrical Engineering or Computer EngineeringBachelor's or Master's in Electrical Engineering or Computer Engineering
Work EnvironmentDesigning custom silicon chips for manufacturingDeveloping programmable logic devices for prototyping and applications
Industry UsageSemiconductor companies, chip manufacturers
Work FocusCreating permanent, optimized chip designsImplementing flexible, reconfigurable logic solutions

Full Time Asic Design and Full Time FPGA Design roles share similar educational backgrounds and industry environments. However, Asic Design focuses on creating permanent, optimized chips for mass production, while FPGA Design involves developing reconfigurable logic devices for testing and specific applications. Both roles are essential in the semiconductor industry but serve different purposes in hardware development.

What cities are hiring for Full Time Asic Design jobs? Cities with the most Full Time Asic Design job openings:
What are the most commonly searched types of Asic Design jobs? The most popular types of Asic Design jobs are:

Senior ASIC Design Engineer

Cornelis Networks

Boston, MA โ€ข On-site, Remote

Full-time

Medical, Dental, Vision, Life, Retirement, PTO

Re-posted yesterday


Job description

At Cornelis we're building the future of AI and HPC networking with an AI-first approach to silicon and software development. We're seeking engineers who are energized by working on cutting-edge ASIC design and distributed software systems, and who are motivated to push the boundaries on how AI can transform everything from chip architecture to system performance at scale.


Cornelis Networks delivers the world's highest performance scale-out networking solutions for AI and HPC datacenters. Our differentiated architecture seamlessly integrates hardware, software and system level technologies to maximize the efficiency of GPU, CPU and accelerator-based compute clusters at any scale. Our solutions drive breakthroughs in AI & HPC workloads, empowering our customers to push the boundaries of innovation. Backed by top-tier venture capital and strategic investors, we are committed to innovation, performance and scalability - solving the world's most demanding computational challenges with our next-generation networking solutions.

We are a fast-growing, forward-thinking team of architects, engineers, and business professionals with a proven track record of building successful products and companies. As a global organization, our team spans multiple U.S. states and six countries, and we continue to expand with exceptional talent in onsite, hybrid, and fully remote roles.


Cornelis Networks is seeking talented Senior ASIC Design Engineers with deep expertise in one or more of the critical areas needed to develop world-class SoCs for deployment in high-performance computing, advanced data analytics, and AI interconnect solutions. Ideal candidates will have relevant experience in the networking domain, with proven expertise in 50G, 100G, and 400G Ethernet protocols-including TCP/IP, RDMA/RoCE, and IPSec-and their application in high-speed data processing and networking environments.


Key Responsibilities:

  • Implement RTL designs using Verilog/System Verilog for high-speed data paths and packet processing logic.
  • Collaborate with verification engineers to create block- and system-level test plans to ensure comprehensive design coverage.
  • Define timing constraints for RTL blocks and work with Physical Design engineers to optimize timing closure.
  • Support post-silicon validation, collaborating with hardware, firmware, and software teams to debug and resolve ASIC issues.
  • Contribute to performance optimization and power-aware design strategies for Host Fabric Interface subsystems.


MinimumQualifications:

  • B.S. or M.S. degree in Computer Engineering, Electrical Engineering, or related field.
  • 8+ years of post-college experience in digital design with proficiency in Verilog and System Verilog.
  • Experience in RTL design for high-speed data paths or packet processing in ASICs.
  • Deep understanding of Host Ethernet adaptor architectures.
  • Familiarity with timing closure and modern physical design methodologies.
  • Proven ability in system-level debug and root cause analysis of technical issues.
  • Strong verbal and written communication skills.


Preferred Qualifications:

  • Knowledge of Ethernet architecture and networking protocols.
  • Prior experience with RTL development for Ethernet host adapters and system debug.
  • Expertise in multiple clock domain designs and asynchronous interfaces.
  • 5+ years of experience with scripting languages such as TCL, Python, or Perl.
  • Familiarity with EDA tools like Design Compiler, Spyglass, or PrimeTime.


Location: This is a remote position for employees residing within the United States.


We offer a competitive compensation package that includes equity, cash, and incentives, along with health and retirement benefits. Our dynamic, flexible work environment provides the opportunity to collaborate with some of the most influential names in the semiconductor industry.

At Cornelis Networks your base salary is only one component of your comprehensive total rewards package. Your base pay will be determined by factors such as your skills, qualifications, experience, and location relative to the hiring range for the position. Depending on your role, you may also be eligible for performance-based incentives, including an annual bonus or sales incentives.

In addition to your base pay, you'll have access to a broad range of benefits, including medical, dental, and vision coverage, as well as disability and life insurance, a dependent care flexible spending account, accidental injury insurance, and pet insurance. We also offer generous paid holidays, 401(k) with company match, and Open Time Off (OTO) for regular full-time exempt employees. Other paid time off benefits include sick time, bonding leave, and pregnancy disability leave.

Cornelis Networks does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. Cornelis Networks is an equal opportunity employer, and all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity or expression, pregnancy, age, national origin, disability status, genetic information, protected veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.