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Asic Intern Jobs (NOW HIRING)

Etched

PD Intern

San Jose, CA · On-site

Job Summary As a Physical Design intern for Etched, you will be responsible for realizing our ... Exposure to ASIC or SoC design concepts * Familiarity with SystemVerilog, UVM, or Python

Etched

RTL Intern

San Jose, CA · On-site

Job Summary As an RTL Intern at Etched, you will help design microarchitecture and implement logic ... Exposure to ASIC or SoC design concepts * Familiarity with SystemVerilog, UVM, or Python

Etched

DV Intern

San Jose, CA · On-site

Job Summary As a Design Verification intern, you will ensure the custom IPs powering our chips ... Exposure to ASIC or SoC design concepts * Familiarity with SystemVerilog, UVM, or Python

Etched

PD Intern

San Jose, CA · On-site

Job Summary As a Physical Design intern for Etched, you will be responsible for realizing our ... Exposure to ASIC or SoC design concepts * Familiarity with SystemVerilog, UVM, or Python

Etched

RTL Intern

San Jose, CA · On-site

Job Summary As an RTL Intern at Etched, you will help design microarchitecture and implement logic ... Exposure to ASIC or SoC design concepts * Familiarity with SystemVerilog, UVM, or Python

Ambarella

AI Vision Processors For Edge Applications Our solutions make cameras smarter by extracting valuable data from high-resolution video streams. Position Responsibilities: * Designing and implementing ...

Teledyne

RTL Design Engineering Intern

Camarillo, CA

$50K - $67K/yr

Join Teledyne Imaging Sensors as an RTL Design Engineering Intern Are you ready to launch your ... Exposure to FPGA development or ASIC design flows * Interest in infrared imaging, optics, or sensor ...

SAAZ Micro Inc

Digital IC Design Intern

Camarillo, CA · On-site

Should be able to work independently to develop RTL designs and synthesize for various FPGA and ASIC platforms. Should be able to work with processors, develop algorithms, and optimize instruction ...

SAAZ Micro Inc

Digital IC Design Intern

Camarillo, CA · On-site

$5K/mo

Should be able to work independently to develop RTL designs and synthesize for various FPGA and ASIC platforms. Should be able to work with processors, develop algorithms, and optimize instruction ...

Teledyne

RTL Design Engineering Intern

Camarillo, CA · On-site

$50K - $67K/yr

Join Teledyne Imaging Sensors as an RTL Design Engineering Intern Are you ready to launch your ... Exposure to FPGA development or ASIC design flows * Interest in infrared imaging, optics, or sensor ...

Advantest

Software R&D Engineer Intern

San Jose, CA · On-site

Excellent teamwork and interpersonal skills; ability to work as part of a multi-disciplinary team (HW, ASIC/FPGA, SW and Mechanical design engineers) * Analytical approach to Problem Solving * ATE ...

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How much do asic intern jobs pay per hour?

As of Jun 6, 2026, the average hourly pay for asic intern in the United States is $19.38, according to ZipRecruiter salary data. Most workers in this role earn between $14.42 and $21.63 per hour, depending on experience, location, and employer.

What are the key skills and qualifications needed to thrive in the Asic Intern position, and why are they important?

To thrive as an ASIC Intern, you need a solid understanding of digital design fundamentals, hardware description languages (such as Verilog or VHDL), and coursework or experience in electrical or computer engineering. Familiarity with tools like simulation software (ModelSim, Synopsys VCS), FPGA prototyping platforms, and version control systems (Git) is typically required. Attention to detail, problem-solving skills, and the ability to collaborate effectively with engineering teams will help you stand out. These competencies are crucial because ASIC design is a complex, team-oriented process that relies on both technical acumen and strong interpersonal skills to ensure successful chip development.

What is an ASIC Intern job?

An ASIC Intern assists in the design, verification, and testing of Application-Specific Integrated Circuits (ASICs). They work with design engineers to create and simulate circuit layouts, debug hardware, and optimize performance. Responsibilities may include using hardware description languages (HDLs) like Verilog or VHDL, writing test scripts, and analyzing power and timing constraints. This role provides hands-on experience in chip development, allowing interns to apply theoretical knowledge to real-world semiconductor projects.

What kind of projects and daily tasks can I expect as an ASIC Intern?

As an ASIC Intern, you can expect to contribute to various stages of the chip development process, including RTL design, verification, simulation, and debugging. Your daily tasks may involve writing and testing code, running simulations, documenting results, and collaborating with senior engineers to resolve technical challenges. It's common to participate in team meetings to discuss project progress and receive feedback on your work, providing valuable exposure to industry best practices. This hands-on experience not only develops your technical skills but also helps you understand the workflow and expectations in a professional ASIC design environment.

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Asic Intern jobs near you
Infographic showing various Asic Intern job openings in the United States as of May 2026, with employment types broken down into 26% Internship, 1% As Needed, and 73% Full Time. Highlights an 86% Physical, 9% Hybrid, and 5% Remote job distribution, with an average salary of $40,304 per year, or $19.4 per hour.

PD Intern

Etched

San Jose, CA • On-site

Internship

Posted 28 days ago

Job description

About Etched
Etched is building the world's first AI inference system purpose-built for transformers - delivering over 10x higher performance and dramatically lower cost and latency than a B200. With Etched ASICs, you can build products that would be impossible with GPUs, like real-time video generation models and extremely deep & parallel chain-of-thought reasoning agents. Backed by hundreds of millions from top-tier investors and staffed by leading engineers, Etched is redefining the infrastructure layer for the fastest growing industry in history.
Job Summary
As a Physical Design intern for Etched, you will be responsible for realizing our front-end designs in silicon, helping Etched to improve iteration speed to final signoff. You will assist in developing and running Physical Design flows to synthesize blocks, automate final design checks, and advise RTL design decisions. We are looking for Fall '26, Spring '27, and Summer '27 interns.
You may be a good fit if you have
  • Progress towards a Bachelor's, Master's, or PhD degree in electrical engineering, computer engineering, or a related field.
  • Familiarity with high-speed digital logic
  • Exposure to ASIC or SoC design concepts
  • Familiarity with SystemVerilog, UVM, or Python
  • Familiarity with verification work and writing test benches
  • Familiarity with physical design flows and tooling
  • Are able to learn quickly about transformers and other aspects of modern artificial intelligence

Strong candidates may also have experience with
  • Familiarity with transformer models and machine learning
  • Familiarity with numerical representations and functions (RTL)
  • Familiarity with clocking and reset schemes (RTL/PD)
  • UVM or formal verification experience (DV)
  • Ability to program with Python or another scripting language

We encourage you to apply even if you do not believe you meet every single qualification.
Program details
  • 12-week paid internship
  • Generous housing support for those relocating
  • Daily lunch and dinner in our office
  • Based at our office in San Jose, CA
  • Direct mentorship from industry leaders and world-class engineers
  • Opportunity to work on one of the most important problems of our time

For any questions, contact internships@etched.com
How we're different
Etched believes in the Bitter Lesson. We think most of the progress in the AI field has come from using more FLOPs to train and run models, and the best way to get more FLOPs is to build model-specific hardware. Larger and larger training runs encourage companies to consolidate around fewer model architectures, which creates a market for single-model ASICs.
We are a fully in-person team in San Jose (Santana Row), and greatly value engineering skills. We do not have boundaries between engineering and research, and we expect all of our technical staff to contribute to both as needed.

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