ZipRecruiter

Log In

1

Asic Intern Jobs in California (NOW HIRING)

Etched

DFT Intern

San Jose, CA · On-site

$17.50 - $23.50/hr

Job Summary As a DFT Intern at Etched, you will help review and refine DFT flow automation to ... Exposure to ASIC or SoC design concepts * Familiarity with digital logic design fundamentals

Etched

DFT Intern

San Jose, CA · On-site

$17.50 - $23.50/hr

Job Summary As a DFT Intern at Etched, you will help review and refine DFT flow automation to ... Exposure to ASIC or SoC design concepts * Familiarity with digital logic design fundamentals

Etched

SI/PI Intern

San Jose, CA · On-site

Job Summary As a Signal Integrity / Power Integrity Intern, you will help design and validate the ... You will work closely with package, PCB, ASIC, and system engineers to analyze high-speed ...

Etched

SI/PI Intern

San Jose, CA · On-site

Job Summary As a Signal Integrity / Power Integrity Intern, you will help design and validate the ... You will work closely with package, PCB, ASIC, and system engineers to analyze high-speed ...

Etched

PD Intern

San Jose, CA · On-site

Job Summary As a Physical Design intern for Etched, you will be responsible for realizing our ... Exposure to ASIC or SoC design concepts * Familiarity with SystemVerilog, UVM, or Python

Etched

DV Intern

San Jose, CA · On-site

Job Summary As aDesign Verification intern, you will ensure the custom IPs powering our chips ... Exposure to ASIC or SoC design concepts * Familiarity with SystemVerilog, UVM, or Python

Etched

PD Intern

San Jose, CA · On-site

Job Summary As a Physical Design intern for Etched, you will be responsible for realizing our ... Exposure to ASIC or SoC design concepts * Familiarity with SystemVerilog, UVM, or Python

Etched

DV Intern

San Jose, CA · On-site

Job Summary As a Design Verification intern, you will ensure the custom IPs powering our chips ... Exposure to ASIC or SoC design concepts * Familiarity with SystemVerilog, UVM, or Python

Etched

RTL Intern

San Jose, CA · On-site

Job Summary As an RTL Intern at Etched, you will help design microarchitecture and implement logic ... Exposure to ASIC or SoC design concepts * Familiarity with SystemVerilog, UVM, or Python

Etched

RTL Intern

San Jose, CA · On-site

Job Summary As an RTL Intern at Etched, you will help design microarchitecture and implement logic ... Exposure to ASIC or SoC design concepts * Familiarity with SystemVerilog, UVM, or Python

next page

Showing results 1-20

All JobsAsic Intern JobsAsic Intern Jobs in California

Asic Intern information

What are the key skills and qualifications needed to thrive in the ASIC intern position, and why are they important?

To thrive as an ASIC Intern, you need a solid understanding of digital design fundamentals, hardware description languages (such as Verilog or VHDL), and coursework or experience in electrical or computer engineering. Familiarity with tools like simulation software (ModelSim, Synopsys VCS), FPGA prototyping platforms, and version control systems (Git) is typically required. Attention to detail, problem-solving skills, and the ability to collaborate effectively with engineering teams will help you stand out. These competencies are crucial because ASIC design is a complex, team-oriented process that relies on both technical acumen and strong interpersonal skills to ensure successful chip development.

What is an ASIC intern?

An ASIC Intern assists in the design, verification, and testing of Application-Specific Integrated Circuits (ASICs). They work with design engineers to create and simulate circuit layouts, debug hardware, and optimize performance. Responsibilities may include using hardware description languages (HDLs) like Verilog or VHDL, writing test scripts, and analyzing power and timing constraints. This role provides hands-on experience in chip development, allowing interns to apply theoretical knowledge to real-world semiconductor projects.

What kind of projects and daily tasks can I expect as an ASIC intern?

As an ASIC Intern, you can expect to contribute to various stages of the chip development process, including RTL design, verification, simulation, and debugging. Your daily tasks may involve writing and testing code, running simulations, documenting results, and collaborating with senior engineers to resolve technical challenges. It's common to participate in team meetings to discuss project progress and receive feedback on your work, providing valuable exposure to industry best practices. This hands-on experience not only develops your technical skills but also helps you understand the workflow and expectations in a professional ASIC design environment.

What are the most commonly searched types of Asic jobs in California?

The most popular types of Asic jobs in California are:

What are popular job titles related to Asic Intern jobs in California?

For Asic Intern jobs in California, the most frequently searched job titles are:

What job categories do people searching Asic Intern jobs in California look for?

The top searched job categories for Asic Intern jobs in California are:

What cities in California are hiring for Asic Intern jobs?

Cities in California with the most Asic Intern job openings:

Asic Intern jobs near you
Infographic showing various Asic Intern job openings in California as of August 2026, with employment types broken down into 20% Internship, 70% Full Time, and 10% Part Time. Highlights an 90% In-person, and 10% Hybrid job distribution.

DFT Intern

Etched

San Jose, CA • On-site

$17.50 - $23.50/hr

Internship

Re-posted 2 days ago

Job description

About Etched
Etched is building hardware for frontier intelligence. We co-design chips, racks, software, and manufacturing to deliver best-in-class throughput and latency across both prefill and decode workloads. Our first products are heavily focused on inference. Backed by hundreds of millions from top-tier investors and staffed by leading engineers, Etched is redefining the infrastructure layer for the fastest growing industry in history.
Job Summary
As a DFT Intern at Etched, you will help review and refine DFT flow automation to support chip-level regression on Caelius. You will work across frontend and backend design teams, contribute to DFT verification (including MBIST, Scan, BSCAN, and SSN simulations), and develop flows for various ATPG fault models. You do not necessarily need prior DFT experience; just the ability to learn quickly in a fast-paced, high-autonomy environment. We are looking for Summer '26, Fall '26, Spring '27, and Summer '27 interns.
You may be a good fit if you have
  • Progress towards a Bachelor's, Master's, or PhD degree in electrical engineering, computer engineering, or a related field.
  • Familiarity with a hardware description language (Verilog or SystemVerilog)
  • Exposure to ASIC or SoC design concepts
  • Familiarity with digital logic design fundamentals
  • Familiarity with standard ASIC design flow steps (synthesis, STA, DFT)
  • Familiarity with scripting in Python, Tcl, or another language
  • Are able to learn quickly about transformers and other aspects of modern artificial intelligence

Strong candidates may also have experience with
  • Knowledge of DFT concepts such as MBIST, scan insertion, and scan compression
  • Experience with Tessent or similar DFT tooling
  • Familiarity with ATPG fault models (SAF, TDF, BDF, IDDQ, PDF)
  • Exposure to DFT flow automation or regression infrastructure
  • Familiarity with clocking and reset schemes

We encourage you to apply even if you do not believe you meet every single qualification.
Program details
  • 12-week paid internship
  • Generous housing support for those relocating
  • Daily lunch and dinner in our office
  • Based at our office in San Jose, CA
  • Direct mentorship from industry leaders and world-class engineers
  • Opportunity to work on one of the most important problems of our time

For any questions, contact internships@etched.com.
How we're different
Etched believes in the Bitter Lesson. We are the first inference-focused frontier AI system. Our addressable market is the entirety of inference, unlike many of our competitors.
We are a fully in-person team in San Jose (Santana Row), and greatly value engineering skills. We do not have boundaries between engineering and research, and we expect all of our technical staff to contribute to both and work across disciplines as needed.

Apply