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Asic Intern Jobs in California (NOW HIRING)

Etched

DFT Intern

San Jose, CA · On-site

$17.50 - $23.50/hr

Job Summary As a DFT Intern at Etched, you will help review and refine DFT flow automation to ... Exposure to ASIC or SoC design concepts * Familiarity with digital logic design fundamentals

Etched

DFT Intern

San Jose, CA · On-site

$17.50 - $23.50/hr

Job Summary As a DFT Intern at Etched, you will help review and refine DFT flow automation to ... Exposure to ASIC or SoC design concepts * Familiarity with digital logic design fundamentals

Etched

SI/PI Intern

San Jose, CA · On-site

Job Summary As a Signal Integrity / Power Integrity Intern, you will help design and validate the ... You will work closely with package, PCB, ASIC, and system engineers to analyze high-speed ...

Etched

SI/PI Intern

San Jose, CA · On-site

Job Summary As a Signal Integrity / Power Integrity Intern, you will help design and validate the ... You will work closely with package, PCB, ASIC, and system engineers to analyze high-speed ...

Etched

PD Intern

San Jose, CA · On-site

Job Summary As a Physical Design intern for Etched, you will be responsible for realizing our ... Exposure to ASIC or SoC design concepts * Familiarity with SystemVerilog, UVM, or Python

Etched

DV Intern

San Jose, CA · On-site

Job Summary As aDesign Verification intern, you will ensure the custom IPs powering our chips ... Exposure to ASIC or SoC design concepts * Familiarity with SystemVerilog, UVM, or Python

Etched

DV Intern

San Jose, CA · On-site

Job Summary As a Design Verification intern, you will ensure the custom IPs powering our chips ... Exposure to ASIC or SoC design concepts * Familiarity with SystemVerilog, UVM, or Python

Etched

PD Intern

San Jose, CA · On-site

Job Summary As a Physical Design intern for Etched, you will be responsible for realizing our ... Exposure to ASIC or SoC design concepts * Familiarity with SystemVerilog, UVM, or Python

Etched

RTL Intern

San Jose, CA · On-site

Job Summary As an RTL Intern at Etched, you will help design microarchitecture and implement logic ... Exposure to ASIC or SoC design concepts * Familiarity with SystemVerilog, UVM, or Python

Etched

RTL Intern

San Jose, CA · On-site

Job Summary As an RTL Intern at Etched, you will help design microarchitecture and implement logic ... Exposure to ASIC or SoC design concepts * Familiarity with SystemVerilog, UVM, or Python

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Asic Intern information

What are the key skills and qualifications needed to thrive in the ASIC intern position, and why are they important?

To thrive as an ASIC Intern, you need a solid understanding of digital design fundamentals, hardware description languages (such as Verilog or VHDL), and coursework or experience in electrical or computer engineering. Familiarity with tools like simulation software (ModelSim, Synopsys VCS), FPGA prototyping platforms, and version control systems (Git) is typically required. Attention to detail, problem-solving skills, and the ability to collaborate effectively with engineering teams will help you stand out. These competencies are crucial because ASIC design is a complex, team-oriented process that relies on both technical acumen and strong interpersonal skills to ensure successful chip development.

What is an ASIC intern?

An ASIC Intern assists in the design, verification, and testing of Application-Specific Integrated Circuits (ASICs). They work with design engineers to create and simulate circuit layouts, debug hardware, and optimize performance. Responsibilities may include using hardware description languages (HDLs) like Verilog or VHDL, writing test scripts, and analyzing power and timing constraints. This role provides hands-on experience in chip development, allowing interns to apply theoretical knowledge to real-world semiconductor projects.

What kind of projects and daily tasks can I expect as an ASIC intern?

As an ASIC Intern, you can expect to contribute to various stages of the chip development process, including RTL design, verification, simulation, and debugging. Your daily tasks may involve writing and testing code, running simulations, documenting results, and collaborating with senior engineers to resolve technical challenges. It's common to participate in team meetings to discuss project progress and receive feedback on your work, providing valuable exposure to industry best practices. This hands-on experience not only develops your technical skills but also helps you understand the workflow and expectations in a professional ASIC design environment.

What are the most commonly searched types of Asic jobs in California?

The most popular types of Asic jobs in California are:

What are popular job titles related to Asic Intern jobs in California?

For Asic Intern jobs in California, the most frequently searched job titles are:

What job categories do people searching Asic Intern jobs in California look for?

The top searched job categories for Asic Intern jobs in California are:

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Infographic showing various Asic Intern job openings in California as of August 2026, with employment types broken down into 20% Internship, 70% Full Time, and 10% Part Time. Highlights an 90% In-person, and 10% Hybrid job distribution.

Physical Design Intern

SK hynix memory solutions America Inc.

San Jose, CA • On-site

$35 - $45/hr

Other

This job post has expired 1 day ago. Applications are no longer accepted.

Job description

About the Company:

At SK Hynix Memory Solution, we're at the forefront of semiconductor innovation, developing advanced memory solutions that power everything from smartphones to data centers. As a global leader in DRAM and NAND flash technologies, we drive the evolution of advancing mobile technology, empowering cloud computing, and pioneering future technologies. Our cutting-edge memory technologies are essential in today's most advanced electronic devices and IT infrastructure, enabling enhanced performance and user experiences across the digital landscape.

We're looking for innovative minds to join our mission of shaping the future of technology. At SK Hynix Memory, you'll be part of a team that's pioneering breakthrough memory solutions while maintaining a strong commitment to sustainability. We're not just adapting to technological change - we're driving it, with significant investments in artificial intelligence, machine learning, and eco-friendly solutions and operational practices. As we continue to expand our market presence and push the boundaries of what's possible in semiconductor technology, we invite you to be part of our journey to creating the next generation of memory solutions that will define the future of computing.

About the Role: Join our Physical Design team to help deliver next-generation SSD controller chips. As a Physical Design Intern, you will collaborate with experienced engineers to transform RTL designs into functional physical layouts. You will gain hands-on experience in the complete ASIC flow from synthesis to tape-out, working on real projects in a fast-paced, innovative environment.

Responsibilities:

  • Execute ASIC physical design implementation flows, including floorplanning, placement, clock tree synthesis (CTS), and routing.
  • Perform static timing analysis (STA) and work to resolve setup and hold timing violations.
  • Run and analyze design rule checks (DRC) and layout versus schematic (LVS) checks to ensure design integrity, as well as IR-Drop analysis.
  • Assist in optimizing power, performance, and area (PPA) metrics using industry-standard EDA tools.
  • Developing entire P&R/physical verification/IR-EM flows.
  • Collaborate with front-end design and verification teams to seamlessly integrate RTL changes and resolve physical design constraints.
  • Help generate and maintain physical design scripts, utilities, and documentation for the team.

Minimum Qualifications:

  • Currently pursuing a Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.
  • Foundational understanding of VLSI design concepts, CMOS circuit design, and digital logic.
  • Familiarity with the basic stages of the ASIC physical design flow.
  • Academic or project experience with scripting languages such as Python, Perl, or TCL.
  • Strong analytical and problem-solving skills with a high attention to detail.

Preferred Qualifications:

  • Hands-on coursework or project experience with industry-standard EDA tools (e.g., Synopsys ICC2, Cadence Innovus, or similar).
  • Exposure to Static Timing Analysis (STA) concepts and tools (e.g., PrimeTime, Tempus).
  • Basic understanding of design constraints (SDC) and library exchange formats (LEF/DEF).
  • Knowledge of low-power design techniques and power intent formats (UPF/CPF).
  • Familiarity with AI/LLM tools (e.g., GPT, Copilot) and prompt engineering, with the ability to leverage them to automate EDA scripting, analyze design data, or optimize workflows.


COMPENSATION: $35/hr - $45/hr

Apply