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Remote Soc Design Engineer Jobs in California (NOW HIRING)

MatX is seeking silicon micro-architects and design engineers to join our team as we create best-in ... Remote Perks We work remotely Monday & Friday, supported by home-tech setup, and remote wifi ...

ASIC/SOC CAD Engineer

Mountain View, CA · On-site +1

$175K - $362K/yr

The ASIC/SOC Physically Design CAD Engineer will be responsible for creating and maintaining our CA ... Remote Perks We work remotely Monday & Friday, supported by home-tech setup, and remote wifi ...

... SoC's and GPU's. This position offers the opportunity to have real impact in a multifaceted ... Strong interpersonal skills and ability to work with on-site and remote teams NVIDIA is widely ...

Remote Duration: 3+ months Commitment: 40 hours/week Role Responsibilities * Evaluate digital chip ... Background in CPU , GPU/ML accelerator , networking, memory subsystem, PCIe/high-speed IO , SoC ...

Integrate robotic and remote handling technologies (e.g., manipulators, cameras, cranes, etc.) into ... We are looking for a Hot Cell Design Engineer that is: * Passionate about clean energy, fuel ...

Integrate robotic and remote handling technologies (e.g., manipulators, cameras, cranes, etc.) into ... We are looking for a Hot Cell Design Engineer that is: * Passionate about clean energy, fuel ...

Design Engineer

San Francisco, CA · On-site +1

$160K - $240K/yr

San Francisco, CA or Remote (Americas, UTC-3 to UTC-10) Job Type: Full-Time Experience: 3+ years ... Design engineers at developer tools companies, frontend engineers with strong design instincts ...

US - Remote Job Title: Core Engineering - Design Engineer V PCB Layout Engineer, AR Product Team As a PCB Layout Engineer on Meta's AR Product Team, you will be responsible for driving world-class ...

A temporary remote work exception is approved while our Bay Area and San Diego sites are being ... Collaborating with RF and SOC system architects and chip leads to define requirements for PLLs and ...

MMIC Design Engineer

Menlo Park, CA · On-site +1

$160K - $250K/yr

We are seeking a highly experienced THz IC Design Engineer to join our growing team. In this role, you will be the technical lead in the design and development of cutting-edge mixed-signal ICs. You ...

We are seeking a highly experienced THz IC Design Engineer to join our growing team. In this role, you will be the technical lead in the design and development of cutting-edge mixed-signal ICs. You ...

Design Engineer V

Sunnyvale, CA · On-site +1

$125 - $130/hr

US remote - Onsite work is a possibility, with a strong preference for Sunnyvale, California PCB ... Design Traveler document. Create and modify engineering tool project templates, meta-data ...

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Remote Soc Design Engineer information

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Physical Design Engineer

Physical Design Engineer

Central Business Solutions

San Jose, CA • On-site, Remote

$159K - $164K/yr

Full-time

Posted 12 days ago


Job description

Title: Physical Design Engineer
Location: 100% Remote
Duration: Long Term Contract role

Responsibilities
  • Develop and own physical design implementation of multi-hierarchy low-power designs including physical-aware logic synthesis, design for testability, floorplan, place and route, static timing analysis, IR Drop, EM, and physical verification in advanced technology nodes.
  • Resolve design and flow issues related to physical design, identify potential solutions, and drive execution
  • Deliver physical design of an end-to-end IP or integration of ASIC/SoC design

Minimum Qualifications:
  • Bachelor's degree in Electrical Engineering, with 5 years of relevant physical design experience
  • Strong understanding in the RTL2GDSII flow and design tapeouts in 16nm/14nm or below process technologies
  • Experience with low power implementation, power gating, multiple voltage rails, strong UPF/CPF knowledge.
  • Experience working with most EDA tools like DC/Genus, ICC2/Innovus, Primetime, Redhawk/Voltus, Calibre.

Preferred Qualification:
  • Experience in running physical-aware logic synthesis and achieving optimal synthesis QoR on low power designs
  • Knowledge of static timing analysis and concepts, defining timing constraints and exceptions, corners/voltage definitions.
  • Experience in Block-level and Full-chip floor-planning, power grid planning
  • Experience with custom or regular clock tree synthesis implementation at block level or top level, and clock power reduction techniques.
  • Experience with Python, TCL, Perl programming.