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Ai Chip Design Rtl Jobs in California (NOW HIRING)

Eridu AI

ASIC Chip Design Lead

Saratoga, CA · On-site

$250K - $280K/yr

Today's AI performance is frequently limited by communication bottlenecks. Eridu introduces ... Own RTL blocks end-to-end from specification through signoff * Make timing-, area-, and power-aware ...

OMNIVISION

SoC Design Engineer

Santa Clara, CA · On-site

$156K - $160K/yr

Perform chip bring-up, validation and debugging. Design, integrate and validate data pipeline ... Arithmetic circuit design related to general datapath circuits, ML and AI circuits. * Arithmetic ...

OMNIVISION

SoC Design Engineer

Santa Clara, CA · On-site

$156K - $160K/yr

Perform chip bring-up, validation and debugging. Design, integrate and validate data pipeline ... Arithmetic circuit design related to general datapath circuits, ML and AI circuits. * Arithmetic ...

Socket.dev

Senior RTL Design Engineer, TPU

Sunnyvale, CA · On-site

$163 - $236/hr

Experience with chip management, clocking, reset, and peripherals like I2C, SPI, UART, etc ... In this role, you'll work to shape the future of AI/ML hardware acceleration. You will have an ...

OMNIVISION

SoC Design Engineer

Santa Clara, CA · On-site

Perform chip bring-up, validation and debugging. Design, integrate and validate data pipeline ... Arithmetic circuit design related to general datapath circuits, ML and AI circuits. * Arithmetic ...

Google

RTL Design Engineer, TPU

Sunnyvale, CA · On-site

Experience with chip management, clocking, reset, and peripherals like I2C, SPI, UART, etc ... About the job In this role, you'll work to shape the future of AI/ML hardware acceleration. You ...

Google

Senior RTL Design Engineer, TPU

Sunnyvale, CA · On-site

Experience with chip management, clocking, reset, and peripherals like I2C, SPI, UART, etc ... About the job In this role, you'll work to shape the future of AI/ML hardware acceleration. You ...

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Ai Chip Design Rtl information

What is an AI Chip Design RTL engineer?

AI Chip Design RTL (Register Transfer Level) engineers are specialists who design the digital logic for chips used in artificial intelligence applications. They use hardware description languages like Verilog or VHDL to create and validate the architecture and functionality of these chips before they are manufactured. Their work ensures that AI processors are efficient, high-performing, and meet the requirements of modern AI workloads. RTL engineers collaborate closely with verification, software, and hardware teams to optimize chip performance and power consumption.

What skills and qualifications are needed to thrive as an AI Chip Design RTL engineer?

To thrive as an AI Chip Design RTL Engineer, you need a solid background in digital design, computer architecture, and proficiency in Hardware Description Languages (HDLs) like Verilog or VHDL, often supported by a degree in electrical or computer engineering. Experience with simulation tools (e.g., ModelSim, Synopsys), ASIC/FPGA design flows, and relevant certifications are highly valued. Strong problem-solving abilities, attention to detail, and effective teamwork and communication skills help you excel in collaborative and complex design environments. These competencies are crucial for creating efficient, reliable AI hardware that meets performance and power requirements in a fast-evolving field.

What are common challenges faced by AI Chip Design RTL engineers during the verification process?

AI Chip Design RTL engineers often encounter challenges in ensuring their designs meet complex functional and performance requirements, especially given the rapid pace of AI hardware advancements. Verification can be particularly demanding due to the need to simulate and test intricate AI workloads, manage large datasets, and debug subtle timing or logic errors. Collaboration with verification teams, system architects, and software engineers is essential to address these issues efficiently and to ensure seamless integration of the RTL code into the broader chip design. Staying up-to-date with the latest verification tools and methodologies is also crucial for success in this role.

What is the difference between Ai Chip Design Rtl vs Ai Chip Verification Engineer?

AspectAi Chip Design RtlAi Chip Verification Engineer
Primary FocusDeveloping and implementing Register Transfer Level (RTL) code for AI chipsVerifying and validating RTL designs to ensure functionality
Skills RequiredHDL languages (Verilog/VHDL), digital design, FPGA/ASIC knowledgeSimulation, testbench creation, debugging, scripting skills
Work EnvironmentDesign teams, hardware development labs, EDA toolsVerification teams, simulation environments, test setups
CertificationsHardware design certifications, FPGA/ASIC trainingVerification methodologies, UVM, SystemVerilog certifications

While Ai Chip Design Rtl focuses on creating the hardware description code for AI chips, Ai Chip Verification Engineer ensures that the RTL design functions correctly through rigorous testing. Both roles require knowledge of HDL languages and work closely within hardware development teams, but their core responsibilities differ—design versus verification.

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Ai Chip Design Rtl jobs near you
Infographic showing various Ai Chip Design Rtl job openings in California as of August 2026, with employment types broken down into 91% Full Time, 6% Part Time, and 3% Contract. Highlights an 82% Physical, 5% Hybrid, and 13% Remote job distribution.

Chip Design and Verification Methodology Engineer

TenX Semi

San Francisco, CA • On-site

$150 - $190/hr

Other

Posted 5 days ago

Job description

Chip Design and Verification Methodology Engineer

San Francisco Bay Area, CA · Hybrid · Full-time

We are looking for a Chip Design and Verification Methodology Engineer who develops innovative methodologies to design and verify chip designs with a massive boost in productivity and quality. We treat verification as a design discipline in a holistic manner—not just a testing phase.

In this role, you will ensure the functional correctness of AI-generated RTL while fundamentally changing the way we design and verify chips. You will architect the verification loop that performs maximal automation, finds the "impossible" bugs, proves correctness, and lays the foundation for improving power-performance-area (PPA) rapidly. Your work is the foundation that makes AI-generated chip design usable and trustworthy.

What You Will Do
  • Drive Verification Methodology and Environment: Take responsibility for the full verification lifecycle of AI-generated RTL with maximal automation. You will build the verification loop that catches bugs, generates actionable feedback, and enables AI models to improve.
  • Architect Test Environments: Write clean, modular, and reusable verification environments/harnesses that can scale across customer designs. Your environments will integrate simulation, formal verification, and emulation into a unified flow.
  • Build Convergence Monitoring: Develop systems that track verification progress, measure coverage, and provide guarantees about design correctness. You will define what "done" means for AI-generated designs.
  • Deep-Dive Debugging: Go beyond pass/fail logs. You will build advanced tools to read, parse, and analyze waveforms, tracing signal dependencies to pinpoint the root cause of logic failures and feed actionable information back to AI models.
  • Collaborate on AI Integration: Work closely with AI engineers to ensure verification feedback improves model accuracy. Your understanding of what makes RTL correct will shape how our AI learns.
  • Formal Proof Generation: Develop formal proofs for critical design paths, ensuring that safety‑critical properties hold under all conditions.
What You Bring (Required)
  • Verilog and SystemVerilog Fluency: You have expert-level proficiency in writing Verilog and SystemVerilog. You understand the nuances of the language for both design (RTL) and verification (TB).
  • SystemVerilog Assertions: You have strong experience writing SystemVerilog Assertions. You know how to write concurrent assertions to validate complex temporal protocols.
  • UVM Expertise: You have deep experience with UVM methodology, including constrained‑random verification, functional coverage, and scoreboards.
  • Computer Architecture Fundamentals: You possess a solid understanding of Computer Architecture and Digital Design fundamentals (e.g., pipelines, FSMs, clock domain crossing, memory hierarchy, and coherence protocols).
  • Waveform Analysis: You have proven ability to read and analyze simulation waveforms (using tools like Verdi, SimVision, or DVE) to resolve complex logic issues.
  • Automation Mindset: You have strong Python/scripting skills and a passion for automating everything that can be automated.
Bonus Points (Preferred)
  • Hands‑on experience with commercial formal tools such as JasperGold or VC Formal. Experience with formal apps (Connectivity, CDC, RDC, CSR) is highly desirable.
  • Deep knowledge of standard on‑chip interface protocols like AXI, AHB, APB, CHI, PCIe, or CXL.
  • Experience at EDA vendors (Synopsys, Cadence, Siemens) or leading semiconductor companies (Intel, AMD, NVIDIA, Qualcomm).
  • Background in emulation platforms (Palladium, Veloce, ZeBu).
  • Familiarity with AI/ML concepts and interest in how AI can transform chip design.
  • MS or PhD in Electrical Engineering or Computer Science.
Why Join Us

You will be building the foundation of a new way to design chips. Verification is what makes AI-generated RTL trustworthy—your work enables everything else. You'll work at the intersection of traditional chip verification and cutting‑edge AI, solving problems no one has solved before.

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