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Ai Chip Design Rtl Jobs in California (NOW HIRING)

TenX Semi

Chip Design Engineer

San Francisco, CA · On-site

In this role, you will combine hands-on RTL design with exposure to cutting-edge AI technology. You will help shape how AI and human expertise work together in chip design. Your designs will go into ...

Eridu AI

ASIC Chip Design Lead

Saratoga, CA · On-site

$250K - $280K/yr

Today's AI performance is frequently limited by communication bottlenecks. Eridu introduces ... Own RTL blocks end-to-end from specification through signoff * Make timing-, area-, and power-aware ...

Ricursive

Chip Design Engineer

Palo Alto, CA · On-site

Ricursive Intelligence is a frontier AI Lab focused on building self-improving systems, starting ... Architect Ricursive's RTL-to-GDSII flow across block, subsystem, and full-chip levels, covering ...

Ricursive

Software Engineer, Chip Design

Palo Alto, CA · On-site

Ricrecursive Intelligence is a frontier AI Lab focused on building self-improving systems, starting ... Develop and scale the infrastructure behind our end-to-end RTL-to-GDSII flow, moving beyond ...

Ricursive

RTL and Design Verification Engineer

Palo Alto, CA · On-site

$160K - $195K/yr

We are reinventing chip development and closing the loop between AI and the hardware that fuels it ... We are hiring best‑in‑class engineers and researchers with real depth in RTL and design ...

OMNIVISION

SoC Design Engineer

Santa Clara, CA · On-site

$156K - $160K/yr

Perform chip bring-up, validation and debugging. Design, integrate and validate data pipeline ... Arithmetic circuit design related to general datapath circuits, ML and AI circuits. * Arithmetic ...

OMNIVISION

SoC Design Engineer

Santa Clara, CA · On-site

Perform chip bring-up, validation and debugging. Design, integrate and validate data pipeline ... Arithmetic circuit design related to general datapath circuits, ML and AI circuits. * Arithmetic ...

OMNIVISION

SoC Design Engineer

Santa Clara, CA · On-site

$156K - $160K/yr

Perform chip bring-up, validation and debugging. Design, integrate and validate data pipeline ... Arithmetic circuit design related to general datapath circuits, ML and AI circuits. * Arithmetic ...

Cerebras Systems

Lead RTL Design Engineer

Sunnyvale, CA · On-site

$175K - $275K/yr

Cerebras Systems builds the world's largest AI chip, 56 times larger than GPUs. This architecture ... This role requires deep expertise in RTL design and integration, with a strong focus on delivering ...

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Ai Chip Design Rtl information

What is an AI Chip Design RTL engineer?

AI Chip Design RTL (Register Transfer Level) engineers are specialists who design the digital logic for chips used in artificial intelligence applications. They use hardware description languages like Verilog or VHDL to create and validate the architecture and functionality of these chips before they are manufactured. Their work ensures that AI processors are efficient, high-performing, and meet the requirements of modern AI workloads. RTL engineers collaborate closely with verification, software, and hardware teams to optimize chip performance and power consumption.

What skills and qualifications are needed to thrive as an AI Chip Design RTL engineer?

To thrive as an AI Chip Design RTL Engineer, you need a solid background in digital design, computer architecture, and proficiency in Hardware Description Languages (HDLs) like Verilog or VHDL, often supported by a degree in electrical or computer engineering. Experience with simulation tools (e.g., ModelSim, Synopsys), ASIC/FPGA design flows, and relevant certifications are highly valued. Strong problem-solving abilities, attention to detail, and effective teamwork and communication skills help you excel in collaborative and complex design environments. These competencies are crucial for creating efficient, reliable AI hardware that meets performance and power requirements in a fast-evolving field.

What are common challenges faced by AI Chip Design RTL engineers during the verification process?

AI Chip Design RTL engineers often encounter challenges in ensuring their designs meet complex functional and performance requirements, especially given the rapid pace of AI hardware advancements. Verification can be particularly demanding due to the need to simulate and test intricate AI workloads, manage large datasets, and debug subtle timing or logic errors. Collaboration with verification teams, system architects, and software engineers is essential to address these issues efficiently and to ensure seamless integration of the RTL code into the broader chip design. Staying up-to-date with the latest verification tools and methodologies is also crucial for success in this role.

What is the difference between Ai Chip Design Rtl vs Ai Chip Verification Engineer?

AspectAi Chip Design RtlAi Chip Verification Engineer
Primary FocusDeveloping and implementing Register Transfer Level (RTL) code for AI chipsVerifying and validating RTL designs to ensure functionality
Skills RequiredHDL languages (Verilog/VHDL), digital design, FPGA/ASIC knowledgeSimulation, testbench creation, debugging, scripting skills
Work EnvironmentDesign teams, hardware development labs, EDA toolsVerification teams, simulation environments, test setups
CertificationsHardware design certifications, FPGA/ASIC trainingVerification methodologies, UVM, SystemVerilog certifications

While Ai Chip Design Rtl focuses on creating the hardware description code for AI chips, Ai Chip Verification Engineer ensures that the RTL design functions correctly through rigorous testing. Both roles require knowledge of HDL languages and work closely within hardware development teams, but their core responsibilities differ—design versus verification.

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Ai Chip Design Rtl jobs near you
Infographic showing various Ai Chip Design Rtl job openings in California as of September 2026, with employment types broken down into 1% Internship, 85% Full Time, 11% Part Time, 1% Temporary, and 2% Contract. Highlights an 81% Physical, 4% Hybrid, and 15% Remote job distribution.

Chip Design Engineer

San Francisco, CA • On-site

TenX Semi
See more jobs at TenX Semiexternal

Other

Posted 12 days ago

Job description

San Francisco Bay Area, CA · Hybrid · Full-time

We are looking for a Chip Design Engineer who works on strategic customer engagements, developing custom IP and optimizing designs for power, performance, and area. You will collaborate closely with our AI systems, providing the domain expertise that ensures AI-generated designs meet real-world requirements.

In this role, you will combine hands-on RTL design with exposure to cutting-edge AI technology. You will help shape how AI and human expertise work together in chip design. Your designs will go into production at the world's leading technology companies.

What You Will Do
  • Design RTL for Customer Projects: Implement RTL for strategic customer engagements. You will write clean, synthesizable, timing-aware Verilog/SystemVerilog.
  • Optimize for PPA: Analyze and optimize designs for power, performance, and area. Your optimizations will contribute to royalty-generating designs.
  • Support Synthesis and Timing: Work through synthesis and timing closure. You understand what makes RTL synthesizable and how to fix timing violations.
  • Improve AI-Generated Designs: Review and enhance AI-generated RTL for production quality. Your feedback will improve model accuracy.
  • Develop Reference Implementations: Create high-quality reference designs that become training data for our AI models.
  • Implement Protocol Blocks: Build protocol implementations (PCIe, DDR, AXI, etc.) for customer requirements.
What You Bring (Required)
  • RTL Design Experience: You have 5+ years of experience designing production RTL. You write clean, readable, synthesizable Verilog/SystemVerilog.
  • Micro-Architecture Understanding: You have solid understanding of pipeline design, FSMs, arbitration, and data flow. You can translate architecture specs into RTL.
  • Synthesis Awareness: You have experience with synthesis tools (Design Compiler, Genus). You understand what makes RTL timing-friendly.
  • Debug Skills: You can read waveforms, trace signal paths, and debug complex logic issues. You have experience with Verdi, SimVision, or similar tools.
  • PPA Intuition: You understand power-performance-area tradeoffs. You can make informed design decisions based on PPA goals.
  • Collaborative Mindset: You work well with verification engineers, architects, and AI engineers. You communicate clearly and give/receive feedback well.
Bonus Points (Preferred)
  • Experience at leading semiconductor companies (Intel, AMD, NVIDIA, Qualcomm, Broadcom, Marvell, MediaTek).
  • Protocol implementation experience (PCIe, DDR, AXI, AHB, APB, CHI).
  • Physical design awareness (floor planning, clock tree, routing congestion).
  • Background in accelerator, SoC, or high-performance computing design.
  • Familiarity with AI/ML concepts and interest in AI-assisted design.
  • MS in Electrical Engineering or Computer Science.
Why Join Us

You will be at the forefront of AI-assisted chip design—a fundamental transformation in how chips are built. Your designs will go into production at top tech companies. You'll learn cutting-edge AI while applying your chip design expertise, building skills that will define the future of the industry.

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