Cognichip is seeking a Scientist AI & Chip Design Engineer to work at the intersection of AI/ML and chip design. The role involves building systems to enhance chip design workflows, including data ...
Cognichip is seeking a Scientist AI & Chip Design Engineer to work at the intersection of AI/ML and chip design. The role involves building systems to enhance chip design workflows, including data ...
ASIC Chip Design Lead
Saratoga, CA · On-site
$250K - $280K/yr
Today's AI performance is frequently limited by communication bottlenecks. Eridu introduces ... Own RTL blocks end-to-end from specification through signoff * Make timing-, area-, and power-aware ...
ASIC Chip Design Lead
Saratoga, CA · On-site
$250K - $280K/yr
Today's AI performance is frequently limited by communication bottlenecks. Eridu introduces ... Own RTL blocks end-to-end from specification through signoff * Make timing-, area-, and power-aware ...
RTL Design Engineer - AI Tools
San Francisco, CA · Remote
$100 - $175/hr
Evaluate digital chip design workflows to enhance AI model training and evaluation . * Design and verify RTL components using Verilog/SystemVerilog . * Collaborate with architecture, verification ...
Quick apply
RTL Design Engineer - AI Tools
San Francisco, CA · Remote
$100 - $175/hr
Evaluate digital chip design workflows to enhance AI model training and evaluation . * Design and verify RTL components using Verilog/SystemVerilog . * Collaborate with architecture, verification ...
SoC Design Engineer
Santa Clara, CA · On-site
$156K - $160K/yr
Perform chip bring-up, validation and debugging. Design, integrate and validate data pipeline ... Arithmetic circuit design related to general datapath circuits, ML and AI circuits. * Arithmetic ...
SoC Design Engineer
Santa Clara, CA · On-site
$156K - $160K/yr
Perform chip bring-up, validation and debugging. Design, integrate and validate data pipeline ... Arithmetic circuit design related to general datapath circuits, ML and AI circuits. * Arithmetic ...
SoC Design Engineer
$156K - $160K/yr
Perform chip bring-up, validation and debugging. Design, integrate and validate data pipeline ... Arithmetic circuit design related to general datapath circuits, ML and AI circuits. * Arithmetic ...
SoC Design Engineer
$156K - $160K/yr
Perform chip bring-up, validation and debugging. Design, integrate and validate data pipeline ... Arithmetic circuit design related to general datapath circuits, ML and AI circuits. * Arithmetic ...
Perform chip bring-up, validation and debugging. Design, integrate and validate data pipeline ... Arithmetic circuit design related to general datapath circuits, ML and AI circuits. * Arithmetic ...
Quick apply
Perform chip bring-up, validation and debugging. Design, integrate and validate data pipeline ... Arithmetic circuit design related to general datapath circuits, ML and AI circuits. * Arithmetic ...
SoC Design Engineer
Santa Clara, CA · On-site
$156K - $160K/yr
Perform chip bring-up, validation and debugging. Design, integrate and validate data pipeline ... Arithmetic circuit design related to general datapath circuits, ML and AI circuits. * Arithmetic ...
SoC Design Engineer
Santa Clara, CA · On-site
$156K - $160K/yr
Perform chip bring-up, validation and debugging. Design, integrate and validate data pipeline ... Arithmetic circuit design related to general datapath circuits, ML and AI circuits. * Arithmetic ...
Lead RTL Design Engineer
Sunnyvale, CA · On-site
$175K - $275K/yr
Cerebras Systems builds the world's largest AI chip, 56 times larger than GPUs. Our novel wafer ... This role requires deep expertise in RTL design and integration, with a strong focus on delivering ...
Lead RTL Design Engineer
Sunnyvale, CA · On-site
$175K - $275K/yr
Cerebras Systems builds the world's largest AI chip, 56 times larger than GPUs. Our novel wafer ... This role requires deep expertise in RTL design and integration, with a strong focus on delivering ...
RTL Design Engineer, TPU
Sunnyvale, CA · On-site
Experience with chip management, clocking, reset, and peripherals like I2C, SPI, UART, etc ... About the job In this role, you'll work to shape the future of AI/ML hardware acceleration. You ...
New
RTL Design Engineer, TPU
Sunnyvale, CA · On-site
Experience with chip management, clocking, reset, and peripherals like I2C, SPI, UART, etc ... About the job In this role, you'll work to shape the future of AI/ML hardware acceleration. You ...
New
Our primary focus is AI acceleration. You will design RTL IP with a focus on chip-to-chip high-speed interconnect subsystems. You will have dynamic, multi-faceted responsibilities in areas such as ...
Our primary focus is AI acceleration. You will design RTL IP with a focus on chip-to-chip high-speed interconnect subsystems. You will have dynamic, multi-faceted responsibilities in areas such as ...
Our primary focus is AI acceleration. You will design RTL IP with a focus on chip-to-chip high-speed interconnect subsystems. You will have dynamic, multi-faceted responsibilities in areas such as ...
Our primary focus is AI acceleration. You will design RTL IP with a focus on chip-to-chip high-speed interconnect subsystems. You will have dynamic, multi-faceted responsibilities in areas such as ...
Physical Design Engineer
Sunnyvale, CA · On-site
$230K - $280K/yr
Cerebras Systems builds the world's largest AI chip, 56 times larger than GPUs. Our novel wafer ... You will work closely with the architecture and RTL team to do R&D on novel concepts for 3D ...
Physical Design Engineer
Sunnyvale, CA · On-site
$230K - $280K/yr
Cerebras Systems builds the world's largest AI chip, 56 times larger than GPUs. Our novel wafer ... You will work closely with the architecture and RTL team to do R&D on novel concepts for 3D ...
3D Physical Design Engineer
Sunnyvale, CA · On-site
$150K - $270K/yr
Cerebras Systems builds the world's largest AI chip, 56 times larger than GPUs. Our novel wafer ... You will work closely with the architecture and RTL team to do R&D on novel concepts for 3D ...
3D Physical Design Engineer
Sunnyvale, CA · On-site
$150K - $270K/yr
Cerebras Systems builds the world's largest AI chip, 56 times larger than GPUs. Our novel wafer ... You will work closely with the architecture and RTL team to do R&D on novel concepts for 3D ...
... market and AI. They are seeking a Senior C++ Software Engineer to develop and support ... RTL design knowledge • Strong expertise in modern C++, compiler, build systems, and database. • ...
... market and AI. They are seeking a Senior C++ Software Engineer to develop and support ... RTL design knowledge • Strong expertise in modern C++, compiler, build systems, and database. • ...
Knowledge of the chip design process and methodology for RTL quality. * Ability to present and explain novel methods to users. About the job In this role, you'll work to shape the future of AI/ML ...
Knowledge of the chip design process and methodology for RTL quality. * Ability to present and explain novel methods to users. About the job In this role, you'll work to shape the future of AI/ML ...
... chip design engineers. Responsibilities : • Build and modernize production RTL-to-GDS flow ... NVIDIA is a computing platform company operating at the intersection of graphics, HPC, and AI.
... chip design engineers. Responsibilities : • Build and modernize production RTL-to-GDS flow ... NVIDIA is a computing platform company operating at the intersection of graphics, HPC, and AI.
Senior Front End Design Engineer (Microarchitecture)
Sunnyvale, CA · On-site
$250K - $300K/yr
Cerebras Systems builds the world's largest AI chip, 56 times larger than GPUs. Our novel wafer ... This role requires deep expertise in RTL design and integration, with a strong focus on delivering ...
Senior Front End Design Engineer (Microarchitecture)
Sunnyvale, CA · On-site
$250K - $300K/yr
Cerebras Systems builds the world's largest AI chip, 56 times larger than GPUs. Our novel wafer ... This role requires deep expertise in RTL design and integration, with a strong focus on delivering ...
Candidates with exposure to AI-for-chip-design initiatives or a strong understanding of modern ML ... Integrate seamlessly into customer pipelines across RTL, PD, and architectural stages. * Track ...
Quick apply
Candidates with exposure to AI-for-chip-design initiatives or a strong understanding of modern ML ... Integrate seamlessly into customer pipelines across RTL, PD, and architectural stages. * Track ...
... design, development and deployment of high performant agents' frameworks and tools. • Develop AI ... RTL quickly. • Excellent command of scripting using Python. • Excellent interpersonal skills ...
... design, development and deployment of high performant agents' frameworks and tools. • Develop AI ... RTL quickly. • Excellent command of scripting using Python. • Excellent interpersonal skills ...
More recently, GPU deep learning ignited modern AI - the next era of computing. NVIDIA is a ... Good architecture and RTL design knowledge * Strong expertise in modern C++, compiler, build ...
More recently, GPU deep learning ignited modern AI - the next era of computing. NVIDIA is a ... Good architecture and RTL design knowledge * Strong expertise in modern C++, compiler, build ...
Ai Chip Design Rtl information
What is the difference between Ai Chip Design Rtl vs Ai Chip Verification Engineer?
| Aspect | Ai Chip Design Rtl | Ai Chip Verification Engineer |
|---|---|---|
| Primary Focus | Developing and implementing Register Transfer Level (RTL) code for AI chips | Verifying and validating RTL designs to ensure functionality |
| Skills Required | HDL languages (Verilog/VHDL), digital design, FPGA/ASIC knowledge | Simulation, testbench creation, debugging, scripting skills |
| Work Environment | Design teams, hardware development labs, EDA tools | Verification teams, simulation environments, test setups |
| Certifications | Hardware design certifications, FPGA/ASIC training | Verification methodologies, UVM, SystemVerilog certifications |
While Ai Chip Design Rtl focuses on creating the hardware description code for AI chips, Ai Chip Verification Engineer ensures that the RTL design functions correctly through rigorous testing. Both roles require knowledge of HDL languages and work closely within hardware development teams, but their core responsibilities differ—design versus verification.
What are some common challenges faced by AI Chip Design RTL engineers during the verification process?
AI Chip Design RTL engineers often encounter challenges in ensuring their designs meet complex functional and performance requirements, especially given the rapid pace of AI hardware advancements. Verification can be particularly demanding due to the need to simulate and test intricate AI workloads, manage large datasets, and debug subtle timing or logic errors. Collaboration with verification teams, system architects, and software engineers is essential to address these issues efficiently and to ensure seamless integration of the RTL code into the broader chip design. Staying up-to-date with the latest verification tools and methodologies is also crucial for success in this role.
What are AI Chip Design RTL engineers?
AI Chip Design RTL (Register Transfer Level) engineers are specialists who design the digital logic for chips used in artificial intelligence applications. They use hardware description languages like Verilog or VHDL to create and validate the architecture and functionality of these chips before they are manufactured. Their work ensures that AI processors are efficient, high-performing, and meet the requirements of modern AI workloads. RTL engineers collaborate closely with verification, software, and hardware teams to optimize chip performance and power consumption.
What are the key skills and qualifications needed to thrive as an AI Chip Design RTL Engineer, and why are they important?
To thrive as an AI Chip Design RTL Engineer, you need a solid background in digital design, computer architecture, and proficiency in Hardware Description Languages (HDLs) like Verilog or VHDL, often supported by a degree in electrical or computer engineering. Experience with simulation tools (e.g., ModelSim, Synopsys), ASIC/FPGA design flows, and relevant certifications are highly valued. Strong problem-solving abilities, attention to detail, and effective teamwork and communication skills help you excel in collaborative and complex design environments. These competencies are crucial for creating efficient, reliable AI hardware that meets performance and power requirements in a fast-evolving field.
What are popular job titles related to Ai Chip Design Rtl jobs in California? For Ai Chip Design Rtl jobs in California, the most frequently searched job titles are:
What job categories do people searching Ai Chip Design Rtl jobs in California look for? The top searched job categories for Ai Chip Design Rtl jobs in California are:
What cities in California are hiring for Ai Chip Design Rtl jobs? Cities in California with the most Ai Chip Design Rtl job openings:
Full-time
Posted 11 days ago
Job description
Job Summary:
Cognichip is seeking a Scientist AI & Chip Design Engineer to work at the intersection of AI/ML and chip design. The role involves building systems to enhance chip design workflows, including data generation and ML model training, while collaborating with engineers across different domains.
Responsibilities:
• Build and iterate on data generation (including synthetic data) for chip-design tasks
• Train ML models
• Design robust evaluation methodology
• Integrate with hardware workflows
• Collaborate closely with engineers across AI + hardware + software, and own projects end-to-end
Qualifications:
Required:
• Baseline knowledge in both AI/ML and chip design
• Familiarity with deep learning + data/model development
• Basic understanding of circuit design and SystemVerilog implementations
• Deep strength in at least one of: Data pipelines / data engineering, Reinforcement learning (RL), UVM, Formal verification, SystemVerilog (advanced)
• Collaborative, take initiative, and can lead when needed
• Shown you can do exceptional work
• Built a product or system that people used
• Made major contributions to a respected codebase / repo
• Done meaningful work in a high-performing environment (such as top companies)
• Shipped a standout project end-to-end
• Strong publications—or similarly rigorous proof of ability
• Demonstrated ability to execute at a very high level
Company:
Cognichip is an AI-first deep tech company focused on transforming the semiconductor industry by revolutionizing how chips are designed. Founded in 2024, the company is headquartered in Redwood City, USA, with a team of 51-200 employees. The company is currently Growth Stage.
Cognichip is seeking a Scientist AI & Chip Design Engineer to work at the intersection of AI/ML and chip design. The role involves building systems to enhance chip design workflows, including data generation and ML model training, while collaborating with engineers across different domains.
Responsibilities:
• Build and iterate on data generation (including synthetic data) for chip-design tasks
• Train ML models
• Design robust evaluation methodology
• Integrate with hardware workflows
• Collaborate closely with engineers across AI + hardware + software, and own projects end-to-end
Qualifications:
Required:
• Baseline knowledge in both AI/ML and chip design
• Familiarity with deep learning + data/model development
• Basic understanding of circuit design and SystemVerilog implementations
• Deep strength in at least one of: Data pipelines / data engineering, Reinforcement learning (RL), UVM, Formal verification, SystemVerilog (advanced)
• Collaborative, take initiative, and can lead when needed
• Shown you can do exceptional work
• Built a product or system that people used
• Made major contributions to a respected codebase / repo
• Done meaningful work in a high-performing environment (such as top companies)
• Shipped a standout project end-to-end
• Strong publications—or similarly rigorous proof of ability
• Demonstrated ability to execute at a very high level
Company:
Cognichip is an AI-first deep tech company focused on transforming the semiconductor industry by revolutionizing how chips are designed. Founded in 2024, the company is headquartered in Redwood City, USA, with a team of 51-200 employees. The company is currently Growth Stage.