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Ai Chip Design Rtl Jobs (NOW HIRING)

Eridu AI

ASIC Chip Design Lead

Saratoga, CA · On-site

$250K - $280K/yr

Today's AI performance is frequently limited by communication bottlenecks. Eridu introduces ... Own RTL blocks end-to-end from specification through signoff * Make timing-, area-, and power-aware ...

OMNIVISION

SoC Design Engineer

Santa Clara, CA · On-site

$156.85K - $160K/yr

Perform chip bring-up, validation and debugging. Design, integrate and validate data pipeline ... Arithmetic circuit design related to general datapath circuits, ML and AI circuits. * Arithmetic ...

OMNIVISION

SoC Design Engineer

Santa Clara, CA

$156.85K - $160K/yr

Perform chip bring-up, validation and debugging. Design, integrate and validate data pipeline ... Arithmetic circuit design related to general datapath circuits, ML and AI circuits. * Arithmetic ...

OMNIVISION

SoC Design Engineer

Santa Clara, CA

Perform chip bring-up, validation and debugging. Design, integrate and validate data pipeline ... Arithmetic circuit design related to general datapath circuits, ML and AI circuits. * Arithmetic ...

Cerebras

Lead RTL Design Engineer

Sunnyvale, CA

$175K - $275K/yr

Cerebras Systems builds the world's largest AI chip, 56 times larger than GPUs. Our novel wafer ... This role requires deep expertise in RTL design and integration, with a strong focus on delivering ...

Cerebras Systems

Lead RTL Design Engineer

Sunnyvale, CA · On-site

$175K - $275K/yr

Cerebras Systems builds the world's largest AI chip, 56 times larger than GPUs. Our novel wafer ... This role requires deep expertise in RTL design and integration, with a strong focus on delivering ...

Apple

GPU Physical Design Engineer

Austin, TX · On-site

$134.80K - $138.80K/yr

This role requires a mix of strategic engineering along with hands-on experience in physical design and large chip integration, being responsible for implementing complete chip design from RTL to ...

Apple

GPU Physical Design Engineer

Austin, TX

$134.80K - $138.80K/yr

This role requires a mix of strategic engineering along with hands-on experience in physical design and large chip integration, being responsible for implementing complete chip design from RTL to ...

Apple

GPU Physical Design Engineer

Austin, TX

$134.80K - $138.80K/yr

This role requires a mix of strategic engineering along with hands-on experience in physical design and large chip integration, being responsible for implementing complete chip design from RTL to ...

Apple

GPU Physical Design Engineer

Austin, TX · On-site

$134.80K - $138.80K/yr

This role requires a mix of strategic engineering along with hands-on experience in physical design and large chip integration, being responsible for implementing complete chip design from RTL to ...

Apple

RTL Design Engineer

Waltham, MA · On-site

Are you looking to expand your chip design career and challenge yourself in a technical and multi ... Perl, JSON and Python)Using GenAI tools (e.g., large language models, AI-assisted code generation ...

Apple

RTL Design Engineer

Melbourne, FL · On-site

Are you looking to expand your chip design career and challenge yourself in a technical and multi ... Perl, JSON and Python)Using GenAI tools (e.g., large language models, AI-assisted code generation ...

Apple

RTL Design Engineer

Cary, NC

Are you looking to expand your chip design career and challenge yourself in a technical and multi ... Perl, JSON and Python) Using GenAI tools (e.g., large language models, AI-assisted code generation ...

Apple

RTL Design Engineer

Melbourne, FL

Are you looking to expand your chip design career and challenge yourself in a technical and multi ... Perl, JSON and Python) Using GenAI tools (e.g., large language models, AI-assisted code generation ...

Apple

RTL Design Engineer

Cary, NC · On-site

Are you looking to expand your chip design career and challenge yourself in a technical and multi ... Perl, JSON and Python)Using GenAI tools (e.g., large language models, AI-assisted code generation ...

Apple

RTL Design Engineer

Melbourne, FL · On-site

Are you looking to expand your chip design career and challenge yourself in a technical and multi ... Perl, JSON and Python)Using GenAI tools (e.g., large language models, AI-assisted code generation ...

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Ai Chip Design Rtl information

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$139.4K

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How much do ai chip design rtl jobs pay per year?

As of May 30, 2026, the average yearly pay for ai chip design rtl in the United States is $139,368.00, according to ZipRecruiter salary data. Most workers in this role earn between $136,000.00 and $136,000.00 per year, depending on experience, location, and employer.

What are the key skills and qualifications needed to thrive as an AI Chip Design RTL Engineer, and why are they important?

To thrive as an AI Chip Design RTL Engineer, you need a solid background in digital design, computer architecture, and proficiency in Hardware Description Languages (HDLs) like Verilog or VHDL, often supported by a degree in electrical or computer engineering. Experience with simulation tools (e.g., ModelSim, Synopsys), ASIC/FPGA design flows, and relevant certifications are highly valued. Strong problem-solving abilities, attention to detail, and effective teamwork and communication skills help you excel in collaborative and complex design environments. These competencies are crucial for creating efficient, reliable AI hardware that meets performance and power requirements in a fast-evolving field.

What are some common challenges faced by AI Chip Design RTL engineers during the verification process?

AI Chip Design RTL engineers often encounter challenges in ensuring their designs meet complex functional and performance requirements, especially given the rapid pace of AI hardware advancements. Verification can be particularly demanding due to the need to simulate and test intricate AI workloads, manage large datasets, and debug subtle timing or logic errors. Collaboration with verification teams, system architects, and software engineers is essential to address these issues efficiently and to ensure seamless integration of the RTL code into the broader chip design. Staying up-to-date with the latest verification tools and methodologies is also crucial for success in this role.

What are AI Chip Design RTL engineers?

AI Chip Design RTL (Register Transfer Level) engineers are specialists who design the digital logic for chips used in artificial intelligence applications. They use hardware description languages like Verilog or VHDL to create and validate the architecture and functionality of these chips before they are manufactured. Their work ensures that AI processors are efficient, high-performing, and meet the requirements of modern AI workloads. RTL engineers collaborate closely with verification, software, and hardware teams to optimize chip performance and power consumption.

What is the difference between Ai Chip Design Rtl vs Ai Chip Verification Engineer?

AspectAi Chip Design RtlAi Chip Verification Engineer
Primary FocusDeveloping and implementing Register Transfer Level (RTL) code for AI chipsVerifying and validating RTL designs to ensure functionality
Skills RequiredHDL languages (Verilog/VHDL), digital design, FPGA/ASIC knowledgeSimulation, testbench creation, debugging, scripting skills
Work EnvironmentDesign teams, hardware development labs, EDA toolsVerification teams, simulation environments, test setups
CertificationsHardware design certifications, FPGA/ASIC trainingVerification methodologies, UVM, SystemVerilog certifications

While Ai Chip Design Rtl focuses on creating the hardware description code for AI chips, Ai Chip Verification Engineer ensures that the RTL design functions correctly through rigorous testing. Both roles require knowledge of HDL languages and work closely within hardware development teams, but their core responsibilities differ—design versus verification.

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ASIC Chip Design Lead

Eridu AI

Saratoga, CA • On-site

$250K - $280K/yr

Full-time

Posted 26 days ago

Job description

About Eridu
Eridu is a Silicon Valley-based hardware startup pioneering infrastructure solutions that accelerate AI data centers to deliver Faster AI. Today's AI performance is frequently limited by communication bottlenecks. Eridu introduces multiple industry-first innovations across silicon, packaging, software, and systems to deliver an order of magnitude improvement in performance and unlock greater GPU utilization to speed training job completion times and tokens-per-second for more profitable inference. We do this while simultaneously reducing capital and power costs and improving reliability.
The company's solutions and value proposition have been widely validated by leading hyperscalers.
Eridu has raised over $200M to date including its most recent, oversubscribed Series A round. The company is led by a veteran team of Silicon Valley executives who have delivered multiple billion dollar product lines and led multiple companies to billion dollar exits, including serial entrepreneur Drew Perkins, co-founder of Infinera (NASDAQ: INFN), Lightera (acq. by Ciena), Gainspeed (acq. by Nokia) and Mojo Vision (the world's leading micro-LED company). The company is in execution mode and has a world-class engineering team with decades of experience in state-of-the-art silicon, packaging, optics, software, and systems. Eridu is working with best-in-class supply chain partners including silicon, packaging and systems.
Visit our website eridu.ai to learn more.
Position Overview
We are seeking a hands-on ASIC Chip Design Lead to own chip design execution from micro-architecture through full-chip integration and timing signoff. This role sits between senior individual contributor and technical lead: you will personally drive RTL and micro-architecture while providing execution leadership across design, verification, and physical design teams.
This is a highly technical, roll-up-your-sleeves role for someone who has taken chips to tape-out, understands what breaks late in the cycle, and knows how to drive designs to closure in a fast-paced startup environment.
Responsibilities
Hands-on RTL Development
  • Write, review, and debug production-quality RTL in Verilog/SystemVerilog
  • Own RTL blocks end-to-end from specification through signoff
  • Make timing-, area-, and power-aware design decisions at the RTL and micro-architecture levels
  • Perform detailed code reviews and set a high technical bar for RTL quality
Micro-Architecture Specification
  • Draft detailed micro-architecture specifications derived from architecture documents and feature requirements
  • Translate high-level requirements into implementable pipelines, control logic, datapaths, interfaces, and corner-case handling
  • Clearly define performance, latency, and resource tradeoffs to unblock RTL and verification execution
Physical-Design-Aware Design & Timing Closure
  • Work closely with Physical Design to improve synthesis and place-and-route timing.
  • Iterate on RTL, hierarchy, micro-architecture, and floorplanning to address timing, congestion, and QoR issues
  • Analyze synthesis and P&R reports and proactively drive timing, area, and power improvements
Verification Collaboration & Debug
  • Partner with Design Verification to debug functional and performance issues
  • Review functional and code coverage and provide actionable feedback
  • Own bugs from discovery through fix, validation, and closure
Full-Chip Integration & Signoff
  • Own full-chip RTL integration and block roll-up
  • Run chip-level synthesis, define constraints, and close chip-level timing
  • Deliver timing-clean netlists to Physical Design that meet performance targets
Execution Discipline & Technical Leadership
  • Drive block- and chip-level design checklists as execution quality gates
  • Review checklist status with designers and proactively push closure of open items
  • Continuously refine design methodologies, checklists, and flows based on silicon learnings
  • Lead by technical authority and hands-on execution rather than coordination alone

Qualifications
  • Strong hands-on experience with RTL design and micro-architecture
  • Proven experience with full-chip integration and timing closure
  • Led at least one full-chip tape-out within the last 3 years, with direct responsibility for design signoff and PD handoff
  • Deep understanding of synthesis, static timing analysis, and physical-design collaboration
  • Experience refactoring and restructuring RTL to resolve timing, area, and congestion challenges
  • Comfortable working cross-functionally with architecture, verification, firmware, and physical design teams
  • Demonstrated ability to drive execution in ambiguous, fast-moving environments

Nice to Have
  • Silicon bring-up experience, including post-silicon debug and RTL-to-silicon correlation
  • Hands-on experience defining and refining SDC constraints and improving post-layout timing
  • Knowledge of high-performance networking architectures and Ethernet-based systems
  • Familiarity with Ultra Ethernet and/or UCIe chip-to-chip interconnect protocols
  • Experience with chiplet-based system design

Why Join Us?
At Eridu, you'll have the opportunity to shape the future of AI infrastructure, working with a world-class team on groundbreaking technology that pushes the boundaries of AI performance. Your contributions will directly impact the next generation of AI infrastructure solutions, transforming the performance of AI data centers.
The starting base salary for the selected candidate will be established based on their relevant skills, experience, qualifications, work location, market trends, and the compensation of employees in comparable roles.
Notice to Recruiting Agencies
Eridu does not accept unsolicited resumes or candidate profiles from staffing agencies or third-party recruiters. Any candidate submitted to Eridu without prior written authorization from our recruiting team will be considered unsolicited and will become the property of Eridu. Eridu reserves the right to pursue and hire such candidates without any obligation to pay fees. Recruiting agencies are expressly instructed not to contact hiring managers, employees, or executives regarding open positions.
The pay range for this role is:
250,000 - 280,000 USD per year (Saratoga, CA)

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