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Ai Chip Design Rtl Jobs in Virginia (NOW HIRING)

We're pioneering AI innovation where hardware and software join to create something extraordinary ... Lead or contribute to full-chip execution, block ownership, team leadership, or chip leadership ...

Physical Design Engineer

Bristol, VA · On-site

$80 - $120/hr

We are seeking a Physical Design Engineer to contribute to our next‑generation chip designs. As a ... physical‑aware RTL design. * Work with advanced AI tools and models to improve productivity ...

Cerebras Systems builds the world's largest AI chip, 56 times larger than GPUs. This architecture ... Develop design specifications for new machine learning and linear algebra kernels and mapping to ...

Cerebras Systems builds the world's largest AI chip, 56 times larger than GPUs. This architecture ... The engineer will own electrical design criteria and contribute to the Basis of Design (BoD) for ...

Digital Design SME

Mclean, VA · On-site

$176K - $282K/yr

... methodology and RTL-to-GDS processes. * Familiarity with industry-standard EDA tool suites ... Design entry, synthesis, place-and-route, analysis and optimization, physical verification, chip ...

Digital Design SME

Mclean, VA · On-site

$176K - $282K/yr

... methodology and RTL-to-GDS processes. * Familiarity with industry-standard EDA tool suites ... Design entry, synthesis, place-and-route, analysis and optimization, physical verification, chip ...

Digital Design SME

Mclean, VA · On-site

$176 - $282/hr

... methodology and RTL-to-GDS processes. * Familiarity with industry-standard EDA tool suites ... Design entry, synthesis, place-and-route, analysis and optimization, physical verification, chip ...

... methodology and RTL-to-GDS processes. * Familiarity with industry-standard EDA tool suites ... Design entry, synthesis, place-and-route, analysis and optimization, physical verification, chip ...

Understanding of System-On-Chip (SoC) design with embedded processor on FPGA * Ability to perform application programming on embedded processor is a plus * Identifies opportunities to apply AI for ...

Understanding of System-On-Chip (SoC) design with embedded processor on FPGA * Ability to perform application programming on embedded processor is a plus * Identifies opportunities to apply AI for ...

... chip design. Originating from multiple years of research, our unique AI hardware & software co-design principle and the Dynamic Neural Accelerator ® AI processor IP are geared towards positively ...

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Ai Chip Design Rtl information

What is an AI Chip Design RTL engineer?

AI Chip Design RTL (Register Transfer Level) engineers are specialists who design the digital logic for chips used in artificial intelligence applications. They use hardware description languages like Verilog or VHDL to create and validate the architecture and functionality of these chips before they are manufactured. Their work ensures that AI processors are efficient, high-performing, and meet the requirements of modern AI workloads. RTL engineers collaborate closely with verification, software, and hardware teams to optimize chip performance and power consumption.

What skills and qualifications are needed to thrive as an AI Chip Design RTL engineer?

To thrive as an AI Chip Design RTL Engineer, you need a solid background in digital design, computer architecture, and proficiency in Hardware Description Languages (HDLs) like Verilog or VHDL, often supported by a degree in electrical or computer engineering. Experience with simulation tools (e.g., ModelSim, Synopsys), ASIC/FPGA design flows, and relevant certifications are highly valued. Strong problem-solving abilities, attention to detail, and effective teamwork and communication skills help you excel in collaborative and complex design environments. These competencies are crucial for creating efficient, reliable AI hardware that meets performance and power requirements in a fast-evolving field.

What are common challenges faced by AI Chip Design RTL engineers during the verification process?

AI Chip Design RTL engineers often encounter challenges in ensuring their designs meet complex functional and performance requirements, especially given the rapid pace of AI hardware advancements. Verification can be particularly demanding due to the need to simulate and test intricate AI workloads, manage large datasets, and debug subtle timing or logic errors. Collaboration with verification teams, system architects, and software engineers is essential to address these issues efficiently and to ensure seamless integration of the RTL code into the broader chip design. Staying up-to-date with the latest verification tools and methodologies is also crucial for success in this role.

What is the difference between Ai Chip Design Rtl vs Ai Chip Verification Engineer?

AspectAi Chip Design RtlAi Chip Verification Engineer
Primary FocusDeveloping and implementing Register Transfer Level (RTL) code for AI chipsVerifying and validating RTL designs to ensure functionality
Skills RequiredHDL languages (Verilog/VHDL), digital design, FPGA/ASIC knowledgeSimulation, testbench creation, debugging, scripting skills
Work EnvironmentDesign teams, hardware development labs, EDA toolsVerification teams, simulation environments, test setups
CertificationsHardware design certifications, FPGA/ASIC trainingVerification methodologies, UVM, SystemVerilog certifications

While Ai Chip Design Rtl focuses on creating the hardware description code for AI chips, Ai Chip Verification Engineer ensures that the RTL design functions correctly through rigorous testing. Both roles require knowledge of HDL languages and work closely within hardware development teams, but their core responsibilities differ—design versus verification.

What job categories do people searching Ai Chip Design Rtl jobs in Virginia look for?

The top searched job categories for Ai Chip Design Rtl jobs in Virginia are:

What cities in Virginia are hiring for Ai Chip Design Rtl jobs?

Cities in Virginia with the most Ai Chip Design Rtl job openings:

Infographic showing various Ai Chip Design Rtl job openings in Virginia as of August 2026, with employment types broken down into 81% Full Time, 16% Part Time, and 3% Contract. Highlights an 82% Physical, 5% Hybrid, and 13% Remote job distribution.

Lead Physical Design Engineer

Fractile

Bristol, VA • On-site

$120 - $180/hr

Other

Posted 17 days ago


Job description

Fractile’s mission is to enable a new chapter in the AI revolution. We’re pioneering AI innovation where hardware and software join to create something extraordinary, unlocking the power of the world’s largest language models with speed increases of x100. Our team is rapidly expanding, and we're searching for visionary engineers, scientists, and thinkers who share our passion for pushing boundaries and redefining what's possible. If you're ready to join a dynamic group of innovators shaping AI's future, we want to hear from you!

We are seeking a highly skilled Lead Physical Design Engineer to contribute to our next-generation chip designs. As a Lead Physical Design Engineer, you will be responsible for the end-to-end implementation of complex IC physical designs, from synthesis to sign-off. In this role, you will take on leadership responsibilities across multiple dimensions, including full-chip ownership, leading a team of physical design engineers, and contributing to broader chip-level physical design leadership. You will collaborate with cross-functional teams, including logic design, verification, and process technology, to optimise performance, power, and area (PPA) while ensuring design integrity and manufacturability.

Key Responsibilities
  • Drive the physical implementation of ASIC/SoC designs, including floorplanning, placement, clock tree synthesis (CTS), routing, and sign-off.
  • Lead or contribute to full-chip execution, block ownership, team leadership, or chip leadership, depending on project needs.
  • Work on synthesis, timing analysis (STA), and optimisation to achieve the best PPA metrics.
  • Own power planning and analysis, addressing IR drop, electromigration, and related effects.
  • Ensure design rule check (DRC), layout vs. schematic (LVS), and other physical verification compliance.
  • Collaborate with DFT engineers to integrate design-for-test (DFT) structures into the physical implementation.
  • Develop and improve flows in EDA tools such as Cadence Innovus, Synopsys Fusion Compiler, Mentor Graphics Calibre, and others.
  • Work closely with RTL and architecture teams to drive design feasibility, constraints, and physical-aware RTL design.
  • Mentor junior engineers and contribute to building strong physical design practices across the team.
  • Work with advanced AI tools and models to improve productivity, analysis, and design quality.
Preferred Qualifications
  • Bachelor’s, Master’s, or PhD in Electrical Engineering, Computer Engineering, or a related field.
  • 10+ years of experience in physical design for advanced technology nodes (e.g., 7nm, 5nm, or below).
  • Strong proficiency in EDA tools for place & route, STA, and sign-off.
  • Solid understanding of CMOS technology, semiconductor physics, and process limitations.
  • Expertise in timing closure, signal integrity, IR drop analysis, and formal verification.
  • Proficiency in scripting languages like TCL, Perl, or Python for automation.
  • Proven ability to take ownership of complex designs and drive them to completion.
  • Experience mentoring engineers and leading physical design efforts.
  • Excellent problem-solving skills, communication, and teamwork in a collaborative design environment.
  • Experience in high-performance computing (HPC), AI accelerators, or networking chips.
  • Experience or strong interest in leveraging advanced AI tools and models within engineering workflows.

Fractile is building silicon, systems and software which will redefine the frontier of AI: running the world’s most advanced models at radically higher speed and lower cost. We have an exceptional team across hardware and software capable of bringing about this change, and we are growing fast to meet demand and deliver our product at scale.

How we work
  • Ownership and execution: you will have full agency to drive your work forward
  • Rapid iteration: we all work directly with top leadership to move from idea to hardware on ambitious timelines
  • Full-stack engagement: hardware, software, silicon, and modelling teams all work closely together to create a product with generational impact
  • Optimistic and pragmatic: we possess the will to win, and to do the hard work to get us there
  • Team player mentality: the mission is bigger than any of us, and we have the curiosity and technical focus to see the best idea shipped, no matter who’s it is
About us
  • Founded in 2022, team of 90+ which is expanding rapidly
  • Modern, open offices in London and Bristol
  • Collaborative, problem-solving culture built on deep curiosity, entrepreneurial initiative and technical fluency
Export control and security clearance

Certain roles may involve working on technologies subject to export restrictions. Applicants may be required to undergo additional eligibility checks to ensure compliance with applicable law.

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