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Vice President Asic Design Engineer Jobs in Virginia

FPGA/ASIC Design Engineer

Reston, VA · On-site

$128K - $176.30K/yr

Technicall/Professional Reporting to the Manager, Engineering (ASIC/FPGA), the Design Engineer will be part of the key ASIC/FPGA design team, responsible for the delivery of FPGA/ASICs for high-speed ...

Vice President of Engineering

Roanoke, VA · On-site

$154.30K - $198.90K/yr

Join Us as the Vice President of Engineering at Potter Global Technologies At Potter Global ... Lead and scale the engineering organization, including organizational design, capability ...

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Vice President Asic Design Engineer information

What are the key skills and qualifications needed to thrive as a Vice President ASIC Design Engineer, and why are they important?

To thrive as a Vice President ASIC Design Engineer, you need deep expertise in digital and analog ASIC design, leadership experience, and an advanced degree in electrical engineering or a related field. Proficiency with industry-standard EDA tools (such as Cadence, Synopsys, or Mentor Graphics), knowledge of verification methodologies, and familiarity with semiconductor manufacturing processes are essential. Outstanding strategic thinking, communication, and team management abilities distinguish top performers in this leadership role. These competencies are crucial for driving innovation, ensuring high-quality chip design, and leading multidisciplinary engineering teams to successful project delivery.

How does a Vice President ASIC Design Engineer typically contribute to cross-functional decision-making within an organization?

A Vice President ASIC Design Engineer plays a pivotal role in cross-functional collaboration by bridging the gap between engineering, product management, and executive leadership. They are responsible for aligning ASIC design strategies with business objectives, facilitating communication between technical teams and stakeholders, and ensuring that design decisions support overall company goals. This often involves participating in high-level planning meetings, setting technical direction, and providing expertise during product roadmap discussions. Their leadership ensures that projects stay on schedule, adhere to quality standards, and meet market demands.

What does a Vice President ASIC Design Engineer do?

A Vice President ASIC Design Engineer leads teams in designing and developing Application-Specific Integrated Circuits (ASICs) for various electronic products. This role involves managing engineering teams, setting technical strategy, overseeing project timelines, and ensuring the quality and efficiency of ASIC development. They also collaborate with other departments, such as product management and manufacturing, to deliver chip solutions that meet business and customer needs. Strong technical expertise, leadership skills, and experience in semiconductor engineering are essential for this position.
What are the most commonly searched types of Asic Design Engineer jobs in Virginia? The most popular types of Asic Design Engineer jobs in Virginia are:
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Infographic showing various Vice President Asic Design Engineer job openings in Virginia as of May 2026, with employment types broken down into 91% Full Time, and 9% Part Time. Highlights an 83% Physical, 10% Hybrid, and 7% Remote job distribution.
FPGA/ASIC Design Engineer

FPGA/ASIC Design Engineer

3B Staffing LLC

Reston, VA • On-site

$128K - $176.30K/yr

Full-time

This job post has expired today. Applications are no longer accepted.


Job description

Job Category:
Technicall/Professional
Job Description:
Reporting to the Manager, Engineering (ASIC/FPGA), the Design Engineer will be part of the key ASIC/FPGA design team, responsible for the delivery of FPGA/ASICs for high-speed crypto applications. S/he will architect, implement high speed crypto architectures, on ASICs/Xilinx Zynq/MPSOC class FPGAs, with hands on design/debug with Ethernet, TCP/IP protocols.
L3Harris has state-of-the-art EDA flows/methodologies including Synopsys DC/Primetime/Synplify, Xilinx/Intel/Microchip EDA with HLS, Mentor EDA Family suite : Questa, VIPs, UVM framework, Clock Domain Crossing (CDC), Reset Domain Crossing (RDC), Questa Lint, and Catapult (HLS).
This is a key, high impact role in the organization to ensure robust quality and delivery of communication products for National Security.
Skills/Experience:
Bachelors Degree in Electrical Engineering or equivalent degree, and minimum 4 years of prior relevant experience (or Masters Degree plus 2 years of prior relevant experience) developing, implementing, and verification of high-performance communications/networking ASIC/FPGA products.
Possess an active SECRET Clearance
Experience mapping algorithms and standards (Ethernet, TCP/IP, AXI) to hardware and architecture/system design tradeoffs.
Proficient in VHDL design process and FPGA flow
Knowledge of Ethernet, TCP/IP protocols
Strong logic/board debug, and analytical skills.
Excellent written, verbal, and presentation skills.
A PLUS for prior experience with:
High Level Synthesis (HLS) with Vivado,
Embedded SW C++ (OOP) and System Verilog Assertions (SVA)
Knowledge of high-speed protocols (PCIe, TCP/IP, Ethernet)
VHDL Experience is required for all candidates to be considered.
  • Looking for mid-senior level folks
  • Proficient in VHDL >5 yrs, Xilinx FPGA design EDA- Vivado
  • Must have done hands on multiple complex designs arch/design/verification/Synthesis/STA
  • Big Plus
    • Working with Ethernet protocol (not just instantiating the IP) Is a big plus.
    • Mentor EDA CDC/Lint/AC/RDC

Required Skills:
Derive engineering specifications from system requirements and develop detailed architecture
Execute design (RTL AND/OR HLS (C++ to RTL)) and RTL quality (RDC, CDC, Formal, Lint)
Generate test plans
Perform module level verification, synthesis/STA, Lab debug, SW driven validation on Linux based SOC evaluation boards
Silicon/FPGA bring up, characterization and production ramp/support/collateral
Desired Skills:
Prior experience in Aerospace / Defense
Experience in C++ (OOP)
Experience in Xilinx MPSOC design with writing/debugging with SDKs, BSPs on bare metal/PetaLinux OS.
Experience with High level synthesis (Xilinx Vivado HLS, AND/OR Mentor Calypto).
Experience with Universal Verification Mythology (UVM)
Experience with project leadership and EVM
Degree Requirements:
Bachelors Degree in Electrical Engineering or equivalent degree, and minimum 4 years of prior relevant experience (or Masters Degree plus 2 years of prior relevant experience) developing, implementing, and verification of high-performance communications/networking ASIC/FPGA products.