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Ai Chip Design Rtl Jobs in Virginia (NOW HIRING)

Sparton Corporation

FPGA Developer

Fairfax, VA · On-site

$94K - $156K/yr

... of RTL design for FPGAs in VHDL or Verilog, or System Verilog - knowledge of all 3 strongly ... Implementing AI/ML inference algorithms using Vitis AI * Linux device driver development * Bit ...

Booz Allen Hamilton, Inc.

Embedded FPGA Engineer

Mclean, VA · On-site

$131K - $168K/yr

Experience with porting and adapting vendor RF transceiver reference designs, such as RTL, IP cores ... AI-driven automation for FPGA design, simulation, synthesis, or testing * Master's degree in ...

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Ai Chip Design Rtl information

What is an AI Chip Design RTL engineer?

AI Chip Design RTL (Register Transfer Level) engineers are specialists who design the digital logic for chips used in artificial intelligence applications. They use hardware description languages like Verilog or VHDL to create and validate the architecture and functionality of these chips before they are manufactured. Their work ensures that AI processors are efficient, high-performing, and meet the requirements of modern AI workloads. RTL engineers collaborate closely with verification, software, and hardware teams to optimize chip performance and power consumption.

What skills and qualifications are needed to thrive as an AI Chip Design RTL engineer?

To thrive as an AI Chip Design RTL Engineer, you need a solid background in digital design, computer architecture, and proficiency in Hardware Description Languages (HDLs) like Verilog or VHDL, often supported by a degree in electrical or computer engineering. Experience with simulation tools (e.g., ModelSim, Synopsys), ASIC/FPGA design flows, and relevant certifications are highly valued. Strong problem-solving abilities, attention to detail, and effective teamwork and communication skills help you excel in collaborative and complex design environments. These competencies are crucial for creating efficient, reliable AI hardware that meets performance and power requirements in a fast-evolving field.

What are common challenges faced by AI Chip Design RTL engineers during the verification process?

AI Chip Design RTL engineers often encounter challenges in ensuring their designs meet complex functional and performance requirements, especially given the rapid pace of AI hardware advancements. Verification can be particularly demanding due to the need to simulate and test intricate AI workloads, manage large datasets, and debug subtle timing or logic errors. Collaboration with verification teams, system architects, and software engineers is essential to address these issues efficiently and to ensure seamless integration of the RTL code into the broader chip design. Staying up-to-date with the latest verification tools and methodologies is also crucial for success in this role.

What is the difference between Ai Chip Design Rtl vs Ai Chip Verification Engineer?

AspectAi Chip Design RtlAi Chip Verification Engineer
Primary FocusDeveloping and implementing Register Transfer Level (RTL) code for AI chipsVerifying and validating RTL designs to ensure functionality
Skills RequiredHDL languages (Verilog/VHDL), digital design, FPGA/ASIC knowledgeSimulation, testbench creation, debugging, scripting skills
Work EnvironmentDesign teams, hardware development labs, EDA toolsVerification teams, simulation environments, test setups
CertificationsHardware design certifications, FPGA/ASIC trainingVerification methodologies, UVM, SystemVerilog certifications

While Ai Chip Design Rtl focuses on creating the hardware description code for AI chips, Ai Chip Verification Engineer ensures that the RTL design functions correctly through rigorous testing. Both roles require knowledge of HDL languages and work closely within hardware development teams, but their core responsibilities differ—design versus verification.

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Ai Chip Design Rtl jobs near you
Infographic showing various Ai Chip Design Rtl job openings in Virginia as of August 2026, with employment types broken down into 81% Full Time, 16% Part Time, and 3% Contract. Highlights an 82% Physical, 5% Hybrid, and 13% Remote job distribution.

Sales Engineer - Data Center Infrastructure

Worldwide Mission Critical LLC

Chantilly, VA • On-site

$111K - $145K/yr

Full-time

Posted 8 days ago

Job description

Description:

This position serves as the primary technical advisor supporting potential tenants, including hyperscale cloud, neoscaler, and artificial intelligence (AI) companies, along with their high performance computing (HPC) requirements, throughout the presales lifecycle for Starwood Digital Ventures (SDV) and its operating subsidiary, Worldwide Mission Critical (WWMC). The Sales Engineer partners closely with Sales, Product, Engineering, Design, Construction, Operations, Legal, and Delivery teams to develop scalable colocation and data center infrastructure solutions that align tenant technical requirements with commercial objectives. The role owns the technical solution from initial discovery through contract execution, and is accountable for feasibility, compliance, and a successful handoff to the project delivery team.

Essential Responsibilities and Duties

A. Technical Sales Leadership

• Serve as the technical lead during tenant engagements and sales pursuits.

• Partner with and support SDV and WWMC Executives, helping carry technical sales conversations throughout the pursuit.

• Translate tenant business objectives into technical infrastructure solutions.

• Establish credibility as a trusted advisor for current and future hyperscale cloud, neoscaler, and AI tenants.

• Lead technical discussions with tenant representatives, subject matter experts (SMEs), engineers, and tenant executive stakeholders.

• Support strategic account planning for key tenants.

B. Tenant Discovery and Requirements Gathering

• Stay current with tenant technical design requirements across infrastructure, structural, power, cooling, networking, security, and operations.

• Capture current state and future state infrastructure requirements, including growth projections, rack densities, and geographic locations of interest for future expansion.

• Identify outlier requirements that fall outside WWMC standards early in the sales cycle.

C. Solution Design

Assist the design team in designing both standard and customized data center solutions across Starwood's sites, aligned with the following disciplines.

• Space: buildings and land plots.

• Power Infrastructure: utility feeds, power topology such as Distributed Redundant (DR), Block Redundant (BR), 2N, and 2N+2 configurations, generator redundancy, power to the pod design, centralized versus decentralized UPS, and cooling and pump power redundancy.

• Cooling: air cooled versus water cooled requirements per environment, high density deployments, and liquid cooling readiness including direct to chip (D2C) design and coolant distribution unit (CDU) strategy.

• Connectivity: network power and cooling requirements, external and internal pathway requirements, structured cabling, fiber pathways, meet me room (MMR) architecture, and diverse entry facilities.

• Security: physical security, access control, closed circuit television (CCTV), visitor management, and compliance controls.

• BMS: Building Management System (BMS) and Electrical Power Monitoring System (EPMS) integration, including how tenants want to ingest critical infrastructure data and alarms.

D. Technical Proposal Development

• Respond to technical portions of tenant proposals, including solution narratives.

• Support pricing and commercial proposals in partnership with Sales and Finance.

• Ensure technical accuracy across all tenant facing deliverables.

E. RFI, RFP, and RFQ Support

Own technical responses for Requests for Information (RFI), Requests for Proposal (RFP), Requests for Quote (RFQ), due diligence questionnaires, technical compliance matrices, security questionnaires, sustainability questionnaires, and AI infrastructure assessments. Coordinate responses across Engineering, Operations, Construction, Product, and Legal.

F. Engineering and Cross Functional Coordination

• Collaborate with Data Center Design, Construction, Development, Engineering, Commissioning, and Operations to validate technical feasibility before commitments are made to tenants.

• Project manage the completion of tenant qualification documents, including Owner's Performance Requirements exhibits, Request for Qualifications capability matrices, and Technical Due Diligence (TDD) checklists, coordinating input across engineering, construction, operations, security, and other technical disciplines.

G. Capacity Planning

• Evaluate available inventory and recommend deployment strategies.

• Support campus expansion planning and evaluate power availability and cooling capacity.

• Coordinate phased tenant growth and support reservation planning for hyperscale deployments.

H. Commercial Support

• Partner with Executive Sales leaders to develop solution pricing assumptions and validate technical costs.

• Support contract and lease negotiations, and review tenant redlines affecting technical commitments.

• Explain the commercial impact of design decisions to internal and tenant stakeholders.

I. Hyperscale, Neoscaler, and AI/HPC Tenant Support

Support large scale deployments for hyperscale cloud, neoscaler, and AI tenants, involving multi megawatt campuses, build to suit facilities, powered shell solutions, wholesale colocation, campus expansions, AI infrastructure, graphics processing unit (GPU) deployments, high density compute, and multi region deployments. Coordinate across internal teams so that tenant requirements align with construction schedules and delivery milestones, including current and upcoming GPU platform generations such as NVIDIA Blackwell (GB200 and GB300 Ultra), Vera Rubin, and Feynman.

J. Tenant Success and Delivery Support

Support post contract activities, including technical kickoff meetings, phase turnovers, design validation, tenant onboarding, deployment planning, design change management, technical issue resolution, and expansion and future growth planning.

K. Market Intelligence

Monitor competitor offerings and emerging technologies, identify tenant trends, and provide feedback to Product Management to support go to market initiatives and service enhancements.

Requirements:

Required Qualifications

• Bachelor's degree in Mechanical Engineering, Electrical Engineering, or a related technical discipline, or equivalent practical experience in data center design, construction, or operations.

• A minimum of 3 to 5 years of experience in data center design, construction, commissioning, or operations, presales engineering, or a comparable technical tenant facing role.

• Prior experience working for a data center builder, developer, or colocation provider, in a role that directly supported hyperscale, neoscaler, or AI tenants.

• Experience supporting hyperscale, neoscaler, and AI or HPC tenant deployments, and current generation graphics processing unit (GPU) platforms.

• Working knowledge of critical infrastructure systems, including UPS, switchgear, generators, automatic transfer switch (ATS) and static transfer switch (STS) systems, and PDUs.

• Working knowledge of data center cooling systems, including computer room air handlers (CRAH), computer room air conditioners (CRAC), fan walls (FW), chillers, cooling towers, primary chilled water loops, coolant distribution units (CDUs), and direct to chip (D2C) liquid cooling.

• Demonstrated ability to read and mark up electrical and mechanical single line drawings and floor plans.

• Strong verbal and written communication skills, and comfort presenting to tenant executives, architects, and technical stakeholders.

• Proficiency with AutoCAD, Bluebeam, and the Microsoft Office suite.

Preferred Qualifications

• Professional Engineer (PE) license.

• A data center industry certification, such as the Certified Data Center Professional (CDCP), Certified Data Center Specialist (CDCS), or Certified Data Center Design Professional (CDCDP), or the Accredited Tier Designer (ATD) certification offered through the Uptime Institute.

• Direct to chip liquid cooling experience, including CDU strategy, coolant distribution loop architecture, glycol chemistry, and leak detection, and experience with demarcation (DMARC) point structuring by tenant type.

• Familiarity with compliance and security frameworks relevant to hyperscale, neoscaler, and AI tenants, including ISO 27001, System and Organization Controls (SOC) 1 and SOC 2, Payment Card Industry Data Security Standard (PCI DSS), Health Insurance Portability and Accountability Act (HIPAA), and the Federal Risk and Authorization Management Program (FedRAMP), where applicable.

• Familiarity with industry design standards such as Uptime Institute Tier Standards, the ANSI/TIA 942 data center standard, BICSI, ASHRAE, and NFPA.