ZipRecruiter

Log In

1

Ai Chip Design Rtl Jobs in Columbia, MD (NOW HIRING)

Peraton

Digital Design SME

Mclean, VA · On-site

$176K - $282K/yr

... methodology and RTL-to-GDS processes. * Familiarity with industry-standard EDA tool suites ... Design entry, synthesis, place-and-route, analysis and optimization, physical verification, chip ...

Peraton

Digital Design SME

Mclean, VA · On-site

$176K - $282K/yr

... methodology and RTL-to-GDS processes. * Familiarity with industry-standard EDA tool suites ... Design entry, synthesis, place-and-route, analysis and optimization, physical verification, chip ...

Peraton

Digital Design SME

Mclean, VA · On-site

$176 - $282/hr

... methodology and RTL-to-GDS processes. * Familiarity with industry-standard EDA tool suites ... Design entry, synthesis, place-and-route, analysis and optimization, physical verification, chip ...

Peraton

Digital Design SME

Mclean, VA · On-site

$176K - $282K/yr

... methodology and RTL-to-GDS processes. * Familiarity with industry-standard EDA tool suites ... Design entry, synthesis, place-and-route, analysis and optimization, physical verification, chip ...

EdgeCortix

Product Marketing Director

Arlington, VA · On-site

$180 - $280/hr

... chip design. Originating from multiple years of research, our unique AI hardware & software co-design principle and the Dynamic Neural Accelerator ® AI processor IP are geared towards positively ...

next page

Showing results 1-20

All JobsAi Chip Design Rtl JobsAi Chip Design Rtl Jobs in Columbia, MD

Ai Chip Design Rtl information

See Columbia, MD salary details

$79.9K

$138.3K

$181.1K

How much do ai chip design rtl jobs pay per year?

As of Aug 19, 2026, the average yearly pay for ai chip design rtl in Columbia, MD is $138,308.00, according to ZipRecruiter salary data. Most workers in this role earn between $135,000.00 and $135,000.00 per year, depending on experience, location, and employer.

What is an AI Chip Design RTL engineer?

AI Chip Design RTL (Register Transfer Level) engineers are specialists who design the digital logic for chips used in artificial intelligence applications. They use hardware description languages like Verilog or VHDL to create and validate the architecture and functionality of these chips before they are manufactured. Their work ensures that AI processors are efficient, high-performing, and meet the requirements of modern AI workloads. RTL engineers collaborate closely with verification, software, and hardware teams to optimize chip performance and power consumption.

What skills and qualifications are needed to thrive as an AI Chip Design RTL engineer?

To thrive as an AI Chip Design RTL Engineer, you need a solid background in digital design, computer architecture, and proficiency in Hardware Description Languages (HDLs) like Verilog or VHDL, often supported by a degree in electrical or computer engineering. Experience with simulation tools (e.g., ModelSim, Synopsys), ASIC/FPGA design flows, and relevant certifications are highly valued. Strong problem-solving abilities, attention to detail, and effective teamwork and communication skills help you excel in collaborative and complex design environments. These competencies are crucial for creating efficient, reliable AI hardware that meets performance and power requirements in a fast-evolving field.

What are common challenges faced by AI Chip Design RTL engineers during the verification process?

AI Chip Design RTL engineers often encounter challenges in ensuring their designs meet complex functional and performance requirements, especially given the rapid pace of AI hardware advancements. Verification can be particularly demanding due to the need to simulate and test intricate AI workloads, manage large datasets, and debug subtle timing or logic errors. Collaboration with verification teams, system architects, and software engineers is essential to address these issues efficiently and to ensure seamless integration of the RTL code into the broader chip design. Staying up-to-date with the latest verification tools and methodologies is also crucial for success in this role.

What is the difference between Ai Chip Design Rtl vs Ai Chip Verification Engineer?

AspectAi Chip Design RtlAi Chip Verification Engineer
Primary FocusDeveloping and implementing Register Transfer Level (RTL) code for AI chipsVerifying and validating RTL designs to ensure functionality
Skills RequiredHDL languages (Verilog/VHDL), digital design, FPGA/ASIC knowledgeSimulation, testbench creation, debugging, scripting skills
Work EnvironmentDesign teams, hardware development labs, EDA toolsVerification teams, simulation environments, test setups
CertificationsHardware design certifications, FPGA/ASIC trainingVerification methodologies, UVM, SystemVerilog certifications

While Ai Chip Design Rtl focuses on creating the hardware description code for AI chips, Ai Chip Verification Engineer ensures that the RTL design functions correctly through rigorous testing. Both roles require knowledge of HDL languages and work closely within hardware development teams, but their core responsibilities differ—design versus verification.

What cities near Columbia, MD are hiring for Ai Chip Design Rtl jobs?

Cities near Columbia, MD with the most Ai Chip Design Rtl job openings:

Ai Chip Design Rtl jobs near you
Infographic showing various Ai Chip Design Rtl job openings in Columbia, MD as of August 2026, with employment types broken down into 87% Full Time, 9% Part Time, and 4% Contract. Highlights an 85% Physical, 5% Hybrid, and 10% Remote job distribution, with an average salary of $138,308 per year, or $66.5 per hour.

[India] Senior UCIe Verification Engineer

EdgeCortix

Arlington, VA • On-site

$156K/yr

Full-time

Posted 15 days ago

Job description

Introduction

We are looking for a Senior UCIe Verification Engineer with strong experience in SystemVerilog/UVM-based verification of high-speed interconnects and SoC subsystems. The ideal candidate should have hands-on experience in verifying UCIe (Universal Chiplet Interconnect Express) IP and should have contributed to at least 1–2 successful SoC tape-outs. The role involves developing reusable verification environments, protocol compliance verification, subsystem/SoC integration, and driving verification closure.


About Edgecortix

At Edgecortix we are a deep-tech startup revolutionizing edge computing with artificial intelligence and novel high efficiency silicon on chip design. Originating from multiple years of research, our unique AI hardware & software co-design principle and the Dynamic Neural Accelerator ® AI processor IP are geared towards positively disrupting the rapidly growing artificial intelligence edge hardware space and bring the power of AI and machine learning to all kinds of devices. Our operations are headquartered in Tokyo, Japan, with offices in Singapore, Virginia, California in the US. In addition, we are starting a new Design Center in India, located in Hyderabad.

The Team

As an engineering driven company we are working to define and solve the hardest problems in AI including computer vision, speech, and natural language, geared towards real-time capabilities on small to medium form factor devices. We originated out of multiple years of research, as such at our core we value learning, intellectual curiosity, and self-starters. We have the ambitious goal of enabling cloud-level performance with significantly better energy-efficiency for AI inference at the edge.

Your Role and Responsibilities:

  • Develop and execute comprehensive verification plans for UCIe IP, subsystems, and SoC integration.
  • Build reusable SystemVerilog/UVM verification environments from scratch.
  • Develop constrained-random and directed test scenarios to verify UCIe functionality and protocol compliance.
  • Verify UCIe protocol features, including:
      • Link initialization and training
      • Sideband communication
      • Adapter layer
      • Protocol layer
      • Data transfer and flow control
      • Link power management
      • Error detection and recovery
      • Reset and initialization sequences
  • Verify interoperability between UCIe and upper-layer protocols such as PCIe, CXL, or streaming interfaces.
  • Develop UVM agents, scoreboards, monitors, protocol checkers, and functional coverage models.
  • Write and debug SystemVerilog Assertions (SVA) for protocol compliance and interface checks.
  • Perform coverage analysis and drive functional and code coverage closure.
  • Debug RTL, protocol, and testbench issues using simulation and waveform analysis.
  • Support gate-level simulations, regression execution, and silicon bring-up activities.
  • Collaborate closely with architecture, RTL, DFT, firmware, physical design, and validation teams throughout the product development cycle.


Desired Qualifications:

  • 6–12 years of experience in functional verification using SystemVerilog and UVM.
  • Strong experience in developing complete UVM verification environments from scratch.
  • Good understanding of UCIe architecture and protocol.
  • Experience verifying high-speed serial interfaces or chiplet interconnects.
  • Strong understanding of:
     • AXI4
     • High-speed protocol verification
     • Clock domain crossings (CDC)
     • Reset domain crossings (RDC)
     • Protocol compliance verification
  • Experience with constrained-random, assertion-based, and coverage-driven verification methodologies.
  • Strong experience writing SystemVerilog Assertions (SVA).
  • Experience with gate-level simulation and timing-aware verification.
  • Excellent RTL and protocol debugging skills.
  • Experience in verifying die-to-die interfaces or chiplet-based architectures.
  • Experience with subsystem and SoC-level verification.
  • Experience with emulator-based verification platforms.
  • Exposure to Formal Verification techniques.
  • Familiarity with Continuous Integration (CI/CD) tools such as Jenkins or GitLab CI.
  • Experience with scripting languages such as Python, Perl, or Tcl.
  • Experience with version control systems such as Git.
  • SoC Experience
     • Hands-on experience in 1–2 successful SoC tape-outs.
     • Experience integrating UCIe subsystems into complex SoCs.
     • Exposure to boot flows, clock/reset architecture, power management, and chiplet integration.
     • Experience collaborating with firmware and post-silicon validation teams during bring-up and debug.

What’s in it for you?

Make a difference: you will have the opportunity to join a well-funded fabless AI semiconductor startup that is disrupting the AI software and hardware co-design space. Be an integral part of its growth and momentum.

Benefits and Perks

  • Highly competitive salary and stock options
  • Flex work time
  • Top-tier employee benefits