We're looking for an Advanced ASIC Design Engineer with solid hands-on experience in RTL design and ... We need an RTL designer who understands that correctness has to be established through rigorous ...
We're looking for an Advanced ASIC Design Engineer with solid hands-on experience in RTL design and ... We need an RTL designer who understands that correctness has to be established through rigorous ...
Lead ASIC Digital Design Engineer
Annapolis Junction, MD · On-site
$176K - $187K/yr
We're looking for a skilled Lead ASIC Digital Design Engineer who has meaningful hands-on ... We need an RTL designer at heart -- someone who thinks in architecture and microarchitecture, and ...
Lead ASIC Digital Design Engineer
Annapolis Junction, MD · On-site
$176K - $187K/yr
We're looking for a skilled Lead ASIC Digital Design Engineer who has meaningful hands-on ... We need an RTL designer at heart -- someone who thinks in architecture and microarchitecture, and ...
Lead ASIC Digital Design Engineer
Annapolis Junction, MD · On-site +1
$176K - $187K/yr
Responsibilities for this Position We're looking for a skilled Lead ASIC Digital Design Engineer ... We need an RTL designer at heart - someone who thinks in architecture and microarchitecture, and ...
Lead ASIC Digital Design Engineer
Annapolis Junction, MD · On-site +1
$176K - $187K/yr
Responsibilities for this Position We're looking for a skilled Lead ASIC Digital Design Engineer ... We need an RTL designer at heart - someone who thinks in architecture and microarchitecture, and ...
Senior ASIC Digital Design Engineer
Annapolis Junction, MD · On-site +1
$142K - $150K/yr
Responsibilities for this Position We're looking for an Advanced ASIC Design Engineer with solid ... We need an RTL designer who understands that correctness has to be established through rigorous ...
Senior ASIC Digital Design Engineer
Annapolis Junction, MD · On-site +1
$142K - $150K/yr
Responsibilities for this Position We're looking for an Advanced ASIC Design Engineer with solid ... We need an RTL designer who understands that correctness has to be established through rigorous ...
You will work with digital designers to debug and address back-end related RTL and gate-level ... You will provide leadership and guidance to junior physical design engineers, and contribute to ...
You will work with digital designers to debug and address back-end related RTL and gate-level ... You will provide leadership and guidance to junior physical design engineers, and contribute to ...
You will work with digital designers to debug and address back-end related RTL and gate-level ... You will provide leadership and guidance to junior physical design engineers, and contribute to ...
New
You will work with digital designers to debug and address back-end related RTL and gate-level ... You will provide leadership and guidance to junior physical design engineers, and contribute to ...
New
You will work with digital designers to debug and address back-end related RTL and gate-level ... You will provide leadership and guidance to junior physical design engineers, and contribute to ...
You will work with digital designers to debug and address back-end related RTL and gate-level ... You will provide leadership and guidance to junior physical design engineers, and contribute to ...
You will work with digital designers to debug and address back-end related RTL and gate-level ... You will provide leadership and guidance to junior physical design engineers, and contribute to ...
New
You will work with digital designers to debug and address back-end related RTL and gate-level ... You will provide leadership and guidance to junior physical design engineers, and contribute to ...
New
You will work with digital designers to debug and address back-end related RTL and gate-level ... You will provide leadership and guidance to junior physical design engineers, and contribute to ...
New
You will work with digital designers to debug and address back-end related RTL and gate-level ... You will provide leadership and guidance to junior physical design engineers, and contribute to ...
New
Active Secret (No interim or inactive) STA (Static Timing Analysis) Design Engineer - looking for ... SVN, git Desirable - Experience with RTL synthesis - Digital simulation, formal verification ...
Active Secret (No interim or inactive) STA (Static Timing Analysis) Design Engineer - looking for ... SVN, git Desirable - Experience with RTL synthesis - Digital simulation, formal verification ...
Circuit Design Engineer
Catonsville, MD · On-site
$99K - $225K/yr
Experience with Register Transfer Level (RTL) in circuit design, including RTL design, verification, and timing analysis * Experience with Field Programmable Gate Arrays (FPGAs) * TS/SCI clearance ...
Circuit Design Engineer
Catonsville, MD · On-site
$99K - $225K/yr
Experience with Register Transfer Level (RTL) in circuit design, including RTL design, verification, and timing analysis * Experience with Field Programmable Gate Arrays (FPGAs) * TS/SCI clearance ...
Circuit Design Engineer
Annapolis Junction, MD · On-site
$99K - $225K/yr
Experience with Register Transfer Level (RTL) in circuit design, including RTL design, verification, and timing analysis * Experience with Field Programmable Gate Arrays (FPGAs) * TS/SCI clearance ...
Circuit Design Engineer
Annapolis Junction, MD · On-site
$99K - $225K/yr
Experience with Register Transfer Level (RTL) in circuit design, including RTL design, verification, and timing analysis * Experience with Field Programmable Gate Arrays (FPGAs) * TS/SCI clearance ...
You will work with digital designers to debug and address back-end related RTL and gate-level ... You will provide leadership and guidance to junior physical design engineers, and contribute to ...
You will work with digital designers to debug and address back-end related RTL and gate-level ... You will provide leadership and guidance to junior physical design engineers, and contribute to ...
Programmable Logic Design Engineer - Temporary
$193K - $290K/yr
Experience with RTL design for various signal processing blocks, including but not limited to ... Bachelor's Degree in Electrical Engineering, Computer Engineering or a related field * 5-8 years ...
Programmable Logic Design Engineer - Temporary
$193K - $290K/yr
Experience with RTL design for various signal processing blocks, including but not limited to ... Bachelor's Degree in Electrical Engineering, Computer Engineering or a related field * 5-8 years ...
FPGA/ASIC Design Engineer (Secret) - Reston, VA - 5137
Reston, VA · On-site
$128K - $176K/yr
Bachelor's degree in electrical engineering or equivalent degree, and minimum 4 years of prior ... Execute design (RTL AND/OR HLS (C++ to RTL)) and RTL quality (RDC, CDC, Formal, Lint) * Generate ...
FPGA/ASIC Design Engineer (Secret) - Reston, VA - 5137
Reston, VA · On-site
$128K - $176K/yr
Bachelor's degree in electrical engineering or equivalent degree, and minimum 4 years of prior ... Execute design (RTL AND/OR HLS (C++ to RTL)) and RTL quality (RDC, CDC, Formal, Lint) * Generate ...
DSP/FEC Engineer
Linthicum, MD · On-site
$141K - $164K/yr
DSP/FEC Engineer, Linthicum Heights, MD We are looking for multiple DSP/FEC Engineer candidates at ... Preferred Qualifications: - Familiarity with FPGA and RTL design including hardware description ...
DSP/FEC Engineer
Linthicum, MD · On-site
$141K - $164K/yr
DSP/FEC Engineer, Linthicum Heights, MD We are looking for multiple DSP/FEC Engineer candidates at ... Preferred Qualifications: - Familiarity with FPGA and RTL design including hardware description ...
DSP Communications Engineer
Linthicum, MD · On-site
$141K - $164K/yr
Minimum Qualifications: - Familiarity with FPGA and RTL design including hardware description languages (Verilog, System Verilog, VHDL). - Good knowledge and understanding across various engineering ...
DSP Communications Engineer
Linthicum, MD · On-site
$141K - $164K/yr
Minimum Qualifications: - Familiarity with FPGA and RTL design including hardware description languages (Verilog, System Verilog, VHDL). - Good knowledge and understanding across various engineering ...
Minimum Qualifications: - Familiarity with FPGA and RTL design including hardware description languages (Verilog, System Verilog, VHDL). - Good knowledge and understanding across various engineering ...
Minimum Qualifications: - Familiarity with FPGA and RTL design including hardware description languages (Verilog, System Verilog, VHDL). - Good knowledge and understanding across various engineering ...
ASIC Digital Design Engineer
Annapolis Junction, MD · Hybrid
$114K - $120K/yr
Implement and simulate IP blocks in RTL using SystemVerilog, VHDL, and other languages. * Integrate ... Contribute to all aspects of design success from specification to production. * Apply our ...
ASIC Digital Design Engineer
Annapolis Junction, MD · Hybrid
$114K - $120K/yr
Implement and simulate IP blocks in RTL using SystemVerilog, VHDL, and other languages. * Integrate ... Contribute to all aspects of design success from specification to production. * Apply our ...
FPGA Electrical Engineer
Linthicum, MD · On-site
... design within ASIC/FPGA, create specification documents. - Develop RTL designs using SystemVerilog, with emphasis on DSP and digital communication system blocks (frontend, physical layer, link layer ...
FPGA Electrical Engineer
Linthicum, MD · On-site
... design within ASIC/FPGA, create specification documents. - Develop RTL designs using SystemVerilog, with emphasis on DSP and digital communication system blocks (frontend, physical layer, link layer ...
Junior Rtl Design Engineer information
See Columbia, MD salary details
$33.2K - $40.1K
3% of jobs
$40.1K - $47K
20% of jobs
$48.4K is the 25th percentile. Wages below this are outliers.
$47K - $53.8K
7% of jobs
$53.8K - $60.7K
6% of jobs
$60.7K - $67.5K
12% of jobs
The median wage is $68K / yr.
$67.5K - $74.4K
17% of jobs
$78K is the 75th percentile. Wages above this are outliers.
$74.4K - $81.2K
17% of jobs
$81.2K - $88.1K
7% of jobs
$88.1K - $95K
4% of jobs
$95K - $101.8K
3% of jobs
$101.8K - $108.7K
2% of jobs
$33.2K
$71.3K
$108.7K
How much do junior rtl design engineer jobs pay per year?
What engineers make $300,000 a year?
What is the salary of RTL design engineer?
What are the key skills and qualifications needed to thrive as a Junior RTL Design Engineer, and why are they important?
What engineers make $200,000 a year?
What are Junior RTL Design Engineers?
What is the difference between Junior Rtl Design Engineer vs Digital Design Engineer?
| Aspect | Junior Rtl Design Engineer | Digital Design Engineer |
|---|---|---|
| Required Credentials | Bachelor's in Electrical Engineering or related field; some certifications | Bachelor's or higher in Electrical/Electronic Engineering; certifications vary |
| Work Environment | Design teams in semiconductor or electronics companies | Design and development teams in similar industries |
| Employer & Industry Usage | Commonly employed in chip design, FPGA, ASIC development | Used in digital circuit and system design across industries |
Both roles involve digital circuit design, but Junior Rtl Design Engineers focus more on RTL coding and verification, while Digital Design Engineers may handle broader digital system development. The roles often overlap in skills and work environment, with the main difference being scope and experience level.
What are some common challenges faced by Junior RTL Design Engineers when transitioning from academic projects to industry roles?
What engineer makes $500,000 a year?
Senior ASIC Digital Design Engineer
Annapolis Junction, MD • On-site
Full-time
Re-posted 20 days ago
General Dynamics Mission Systems rating
7.9
Based on 30 frontline employees who took The Breakroom Quiz
127th of 241 rated software companies
Job description
Education Requirements:
Requires a Bachelor’s degree in Electrical or Computer Engineering, or a related Science, Engineering, Technology or Mathematics field. Also requires 5+ years of job-related experience, or a Master's degree plus 3 years of job-related experience.
Clearance Requirements:
Ability to obtain a Department of Defense Secret security clearance is required at time of hire. Applicants selected will be subject to a U.S. Government security investigation and must meet eligibility requirements for access to classified information. Due to the nature of work performed within our facilities, U.S. citizenship is required.
We're looking for an Advanced ASIC Design Engineer with solid hands-on experience in RTL design and a foundational understanding of the full ASIC/FPGA design lifecycle. This is a technical role for someone who is ready to take on meaningful ownership of design tasks within a collaborative, high-performing team.
If your career has been primarily running P&R tools, this probably isn't the right fit. We also need someone who has moved beyond the "burn it and see if it works" model of FPGA development — on ASIC, you don't get that luxury. We need an RTL designer who understands that correctness has to be established through rigorous simulation, formal verification, and independent review long before anything gets near silicon.
The right candidate has worked in larger, structured design environments where verification is a discipline in its own right — with dedicated verification partners, formal review processes, and clear functional closure criteria. A self-starter who can work independently on assigned tasks, drives progress without constant direction, and brings a problem-solving mindset to everything they touch.
What You'll Do
- Own RTL design tasks — Develop RTL with a focus on correctness: bus fabric integrity, clock domain crossings, reset order-of-operations, and design-for-verification
- Contribute to timing closure — Work through synthesis, place and route, and static timing analysis; identify root causes of timing failures and contribute to fixes
- Support verification efforts — Execute test and simulation plans in coordination with a dedicated verification team; understand and work within a formal verification process; verify results and help drive closure on failures
- Participate in JIRA triage — Review incoming issues and help maintain an accurate and actionable backlog
- Participate in code reviews — Engage in RTL code reviews, providing and receiving constructive technical feedback
- Support program planning — Provide input on task status, schedule risk, and level of effort to support IMS and EV reporting
- Support proposals — Contribute to basis of estimates (BOEs) for proposals, providing technical input on scope and level of effort for assigned design tasks
- Support technology evaluation — Assist in assessing foundry technologies, device libraries, IP cores, and EDA tooling
- Collaborate broadly — Participate in Integrated Product Teams and working groups
What We're Looking For
- 5–8+ years of ASIC/FPGA design experience, with meaningful time spent as an RTL designer
- Experience working in larger, structured design teams with formal verification processes and independent verification partners — not solely in small-team or solo development environments
- Demonstrated understanding that design correctness is established through simulation, formal verification, and peer review — not through iteration on hardware
- Some experience contributing to ASIC tape-out efforts is a plus
- Familiarity with FinFET process nodes (7nm, 5nm, or similar) is a differentiator
- Familiarity with commercial foundry flows (TSMC, GlobalFoundries, Samsung, or equivalent)
- Working knowledge of:
- RTL design and microarchitecture
- Bus fabric design and verification
- Clock domain crossing (CDC) analysis
- Reset sequencing and validation
- Timing closure fundamentals
- Power analysis basics
Skills & Knowledge
- Solid understanding of ASIC/FPGA engineering concepts, RTL coding practices, and synthesis flows
- Familiarity with industry-standard EDA tools (synthesis, simulation, formal verification, STA)
- Ability to work independently on assigned tasks while coordinating effectively within the team
- Familiarity with vendor and foundry capabilities
- Proficiency in JIRA for issue tracking and backlog management
- Proficiency in Microsoft Office for documentation and communication
Why This Role
You won't be handed a spec and told to code. You'll take real ownership of design tasks, with exposure across the full ASIC lifecycle and the opportunity to grow alongside experienced engineers. This is a role where your work matters, your initiative is recognized, and the team values engineers who take ownership and see problems through to resolution.
This estimate represents the typical salary range for this position based on experience and other factors (geographic location, etc.). Actual pay may vary. This job posting will remain open until the position is filled.
USD $142,166.00 - USD $150,000.00 /Yr.
General Dynamics Mission Systems (GDMS) engineers a diverse portfolio of high technology solutions, products and services that enable customers to successfully execute missions across all domains of operation. With a global team of 12,000+ top professionals, we partner with the best in industry to expand the bounds of innovation in the defense and scientific arenas. Given the nature of our work and who we are, we value trust, honesty, alignment and transparency. We offer highly competitive benefits and pride ourselves in being a great place to work with a shared sense of purpose. You will also enjoy a flexible work environment where contributions are recognized and rewarded. If who we are and what we do resonates with you, we invite you to join our high-performance team!
Equal Opportunity Employer / Individuals with Disabilities / Protected Veterans
What General Dynamics Mission Systems employees say
Pay
Benefits
Hours and flexibility
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Get the full story on Breakroom
About General Dynamics Mission Systems
Sourced by ZipRecruiter
Industry
Guided missile and space vehicle manufacturing
Company size
10,000+ Employees
Headquarters location
Fairfax, VA, US
Year founded
1952