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Junior Rtl Design Engineer Jobs in Baltimore, MD

Geologics

Mixed Signal Digital Design Engineer

Severn, MD · On-site

$68 - $78/hr

Mixed Signal Digital Design Engineer needed: Severn, MD. Must Be Clearable We have an opening with ... The incumbent will also mentor junior mixed‑signal PCB designers and champion best‑in‑class ...

Geologics

Mixed Signal Digital Design Engineer

Severn, MD · On-site

$68 - $78/hr

Mixed Signal Digital Design Engineer needed: Severn, MD. Must Be Clearable We have an opening with ... The incumbent will also mentor junior mixed‑signal PCB designers and champion best‑in‑class ...

Next Step Systems

DSP/FEC Engineer

Linthicum, MD · On-site

$141K - $164K/yr

DSP/FEC Engineer, Linthicum Heights, MD We are looking for multiple DSP/FEC Engineer candidates at ... Preferred Qualifications: - Familiarity with FPGA and RTL design including hardware description ...

Next Step Systems

DSP Communications Engineer

Linthicum, MD · On-site

$141K - $164K/yr

Minimum Qualifications: - Familiarity with FPGA and RTL design including hardware description languages (Verilog, System Verilog, VHDL). - Good knowledge and understanding across various engineering ...

Johnson Service Group

Be Seen First

Mechanical Design Engineer

Westminster, MD · On-site

$66.67/hr

Senior Mechanical Design Engineer - Composites Pay Rate: $66.67/hr (roughly 126k annual) Location ... Coach junior engineers within the incumbents specified domain. Basic Qualifications: * Bachelor ...

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All JobsJunior Rtl Design Engineer JobsJunior Rtl Design Engineer Jobs in Baltimore, MD

Junior Rtl Design Engineer information

See Baltimore, MD salary details

$33.3K

$71.3K

$108.8K

How much do junior rtl design engineer jobs pay per year?

As of Jun 9, 2026, the average yearly pay for junior rtl design engineer in Baltimore, MD is $71,343.00, according to ZipRecruiter salary data. Most workers in this role earn between $48,200.00 and $79,500.00 per year, depending on experience, location, and employer.

What are the key skills and qualifications needed to thrive as a Junior RTL Design Engineer, and why are they important?

To thrive as a Junior RTL Design Engineer, a solid background in digital logic design, hardware description languages (such as Verilog or VHDL), and a relevant engineering degree are essential. Experience with simulation and synthesis tools (like ModelSim, Synopsys, or Xilinx Vivado) and a basic understanding of ASIC or FPGA flows are typically required. Strong analytical thinking, attention to detail, and effective teamwork skills help individuals excel in translating specifications into efficient hardware designs. These skills ensure accurate, reliable, and high-performance digital circuit development, which is crucial for meeting project goals and industry standards.

What are Junior RTL Design Engineers?

Junior RTL Design Engineers are entry-level professionals who work on designing and verifying the Register Transfer Level (RTL) logic for digital integrated circuits. They typically use hardware description languages like Verilog or VHDL to describe and simulate the functionality of hardware blocks according to specifications. Their responsibilities often include coding, simulation, debugging, and collaborating with senior engineers to ensure the design meets performance and functional requirements. This role is crucial in the process of creating chips and digital systems used in various electronic devices.

What is the difference between Junior Rtl Design Engineer vs Digital Design Engineer?

AspectJunior Rtl Design EngineerDigital Design Engineer
Required CredentialsBachelor's in Electrical Engineering or related field; some certificationsBachelor's or higher in Electrical/Electronic Engineering; certifications vary
Work EnvironmentDesign teams in semiconductor or electronics companiesDesign and development teams in similar industries
Employer & Industry UsageCommonly employed in chip design, FPGA, ASIC developmentUsed in digital circuit and system design across industries

Both roles involve digital circuit design, but Junior Rtl Design Engineers focus more on RTL coding and verification, while Digital Design Engineers may handle broader digital system development. The roles often overlap in skills and work environment, with the main difference being scope and experience level.

What are some common challenges faced by Junior RTL Design Engineers when transitioning from academic projects to industry roles?

Junior RTL Design Engineers often find the transition from academic projects to industry roles challenging due to the increased complexity and scale of commercial designs. In industry, there is a strong emphasis on meeting strict timing, power, and area requirements, as well as adhering to rigorous verification and documentation standards. Collaboration with verification, physical design, and software teams is essential, and juniors may need to quickly adapt to using industry-standard EDA tools and workflows. Gaining proficiency in debugging and understanding legacy codebases are also typical hurdles. However, most teams provide mentorship and structured onboarding to help new engineers succeed.
What are popular job titles related to Junior Rtl Design Engineer jobs in Baltimore, MD? For Junior Rtl Design Engineer jobs in Baltimore, MD, the most frequently searched job titles are:
What job categories do people searching Junior Rtl Design Engineer jobs in Baltimore, MD look for? The top searched job categories for Junior Rtl Design Engineer jobs in Baltimore, MD are:
What cities near Baltimore, MD are hiring for Junior Rtl Design Engineer jobs? Cities near Baltimore, MD with the most Junior Rtl Design Engineer job openings:
Junior Rtl Design Engineer jobs near you
Infographic showing various Junior Rtl Design Engineer job openings in Baltimore, MD as of May 2026, with employment types broken down into 87% Full Time, 11% Part Time, and 2% Contract. Highlights an 85% Physical, 5% Hybrid, and 10% Remote job distribution, with an average salary of $71,343 per year, or $34.3 per hour.

ASIC Static Timing and Synthesis Engineers (00005)

22nd Century Technologies Inc.

Baltimore, MD • On-site

Contractor

Posted 14 days ago

Job description

Company Description
This is Harpal Singh and I am the Staffing Specialist with 22nd Century Technologies Inc. (TSCTI). We are Government Software integrators working with DoD and civilian space and are fast growing company in DoD sector with our Prime Contracts includes DLA, Peace Corp, Dept. of Navy, Dept. of Air Force, NIH, US Army, SSA, IRS, Dept. of Justice, Dept. of the Interior , Dept. of Transportation, Federal Maritime Commission, Broadcasting and over 35 States all over USA.
Find more about us at www.tscti.com .
You can reach me at 908.765.0003 ext. 315 # for any questions, I'm available today till 6 PM EST.
Kindly send me your updated resume along with expected rates at singhh @ tscti.com
Job Description
Client: Northrop Grumman
Position: ASIC Static Timing and Synthesis Engineers (00005)
Work Location: Baltimore, MD
Duration: Long term contract (a year+) or CTH (NG will offer FT opportunity after a year for the right candidate, if candidate is interested)
Clearance: Active Secret (No interim or inactive)
Job Description:
STA (Static Timing Analysis) Design Engineer
- looking for experienced Timing Analysis & Sign-off expert for complex digital design. The engineer will be responsible for owning & working with team on constraint development, timing closure using latest nanometer technologies
Responsibilities
- Work with systems architect/IP experts to develop level timing constraints
- Work with physical design team on design constraint and timing closure
- Be hands-on technical individual contributor
Requirements
- secret government clearance within last 5 years
- good knowledge of EDA tools and scripting
- BSEE with 8 years of experience or MSEE with 5 years' experience in static timing & RTL Design
- Must be a very good team player with a very good oral, written and interpersonal communication skills
Tool experience
- Synopsys Primetime-SI, Synopsys Design Compiler, Cadence Encounter Timing system
- Scripting languages - tcl, csh, perl, Makefile
- Operating systems: linux, window
- Revision control: SVN, git
Desirable
- Experience with RTL synthesis
- Digital simulation, formal verification, linting, test insertion & atpg generation
- Experience with ARM CPUs, peripherals such as I2C, SPI, UART, Asynchronous interface designs, peripherals and interconnect protocols such as AHB, AXI, PCIE etc
- Tool experience - Mentor Questa, Mentor Tessent, Synopsys Formality
Keywords
- STA, SSTA, OCV, Margins, Derates, Sign-off derate, PTV variation, sign-off criteria, STA methodology, sign-off methodology, binning
Qualifications
  • secret government clearance within last 5 years\
  • looking for experienced Timing Analysis & Sign-off expert for complex digital design. The engineer will be responsible for owning & working with team on constraint development, timing closure using latest nanometer technologies

Additional Information
All your information will be kept confidential according to EEO guidelines.

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