ZipRecruiter

Log In

1

Ai Chip Design Rtl Jobs in Portland, OR (NOW HIRING)

ServerLogic

Senior ASIC Design Engineer

Beaverton, OR · On-site

Demonstrate knowledge of Verilog for chip design and verification. * Must understand the ASIC flow from MAS to silicon including RTL design, verification, synthesis, timing constraints, GLS, FPGA ...

Apple

Front-End CAD Methodology Engineer

Beaverton, OR

$129.40K - $177.90K/yr

... chip (SoC). You'll ensure Apple products and services can seamlessly and efficiently handle the ... AI solutions that the design team can use to improve experience working with these RTL Construction ...

Apple

CPU Design Verification Engineer

Beaverton, OR · On-site

$141.50K - $172.70K/yr

In this highly visible role, you will be at the center of a chip design effort collaborating with ... RTL designers on verifying the functional correctness of the design • Develop test plans and test ...

Apple

CPU Design Verification Engineer

Beaverton, OR · On-site

$141.50K - $172.70K/yr

In this highly visible role, you will be at the center of a chip design effort collaborating with ... RTL designers on verifying the functional correctness of the design • Develop test plans and test ...

Apple

CPU Design Verification Engineer

Beaverton, OR · On-site

$141.50K - $172.70K/yr

In this highly visible role, you will be at the center of a chip design effort collaborating with ... RTL designers on verifying the functional correctness of the design • Develop test plans and test ...

Apple

CPU Design Verification Engineer

Beaverton, OR · On-site

$141.50K - $172.70K/yr

In this highly visible role, you will be at the center of a chip design effort collaborating with ... RTL designers on verifying the functional correctness of the design • Develop test plans and test ...

Apple

CPU Design Verification Engineer

Beaverton, OR · On-site

$141.50K - $172.70K/yr

In this highly visible role, you will be at the center of a chip design effort collaborating with ... RTL designers on verifying the functional correctness of the design • Develop test plans and test ...

Apple

CPU Design Verification Engineer

Beaverton, OR · On-site

$141.50K - $172.70K/yr

In this highly visible role, you will be at the center of a chip design effort collaborating with ... RTL designers on verifying the functional correctness of the design • Develop test plans and test ...

Apple

CPU Design Verification Engineer

Beaverton, OR · On-site

$141.50K - $172.70K/yr

In this highly visible role, you will be at the center of a chip design effort collaborating with ... RTL designers on verifying the functional correctness of the design • Develop test plans and test ...

Apple

CPU Design Verification Engineer

Beaverton, OR · On-site

$141.50K - $172.70K/yr

In this highly visible role, you will be at the center of a chip design effort collaborating with ... RTL designers on verifying the functional correctness of the design • Develop test plans and test ...

Intel

RTL Design Engineer

Hillsboro, OR

$105.65K - $200.34K/yr

Develops the logic design, register transfer level (RTL) coding, and simulation for a CPU required to generate cell libraries, functional units, and the CPU IP block for integration in full chip ...

Intel

Senior CPU RTL Design Engineer

Hillsboro, OR · On-site

... chip designs. Participates actively in the definition of architecture and microarchitecture ... Experience with driving front end methodologies and championing the use of automation / AI tools to ...

next page

Showing results 1-20

People also search for

All JobsAi Chip Design Rtl JobsAi Chip Design Rtl Jobs in Portland, OR

Ai Chip Design Rtl information

See Portland, OR salary details

$85.4K

$147.8K

$193.5K

How much do ai chip design rtl jobs pay per year?

As of May 28, 2026, the average yearly pay for ai chip design rtl in Portland, OR is $147,800.00, according to ZipRecruiter salary data. Most workers in this role earn between $144,200.00 and $144,200.00 per year, depending on experience, location, and employer.

What are the key skills and qualifications needed to thrive as an AI Chip Design RTL Engineer, and why are they important?

To thrive as an AI Chip Design RTL Engineer, you need a solid background in digital design, computer architecture, and proficiency in Hardware Description Languages (HDLs) like Verilog or VHDL, often supported by a degree in electrical or computer engineering. Experience with simulation tools (e.g., ModelSim, Synopsys), ASIC/FPGA design flows, and relevant certifications are highly valued. Strong problem-solving abilities, attention to detail, and effective teamwork and communication skills help you excel in collaborative and complex design environments. These competencies are crucial for creating efficient, reliable AI hardware that meets performance and power requirements in a fast-evolving field.

What are some common challenges faced by AI Chip Design RTL engineers during the verification process?

AI Chip Design RTL engineers often encounter challenges in ensuring their designs meet complex functional and performance requirements, especially given the rapid pace of AI hardware advancements. Verification can be particularly demanding due to the need to simulate and test intricate AI workloads, manage large datasets, and debug subtle timing or logic errors. Collaboration with verification teams, system architects, and software engineers is essential to address these issues efficiently and to ensure seamless integration of the RTL code into the broader chip design. Staying up-to-date with the latest verification tools and methodologies is also crucial for success in this role.

What are AI Chip Design RTL engineers?

AI Chip Design RTL (Register Transfer Level) engineers are specialists who design the digital logic for chips used in artificial intelligence applications. They use hardware description languages like Verilog or VHDL to create and validate the architecture and functionality of these chips before they are manufactured. Their work ensures that AI processors are efficient, high-performing, and meet the requirements of modern AI workloads. RTL engineers collaborate closely with verification, software, and hardware teams to optimize chip performance and power consumption.

What is the difference between Ai Chip Design Rtl vs Ai Chip Verification Engineer?

AspectAi Chip Design RtlAi Chip Verification Engineer
Primary FocusDeveloping and implementing Register Transfer Level (RTL) code for AI chipsVerifying and validating RTL designs to ensure functionality
Skills RequiredHDL languages (Verilog/VHDL), digital design, FPGA/ASIC knowledgeSimulation, testbench creation, debugging, scripting skills
Work EnvironmentDesign teams, hardware development labs, EDA toolsVerification teams, simulation environments, test setups
CertificationsHardware design certifications, FPGA/ASIC trainingVerification methodologies, UVM, SystemVerilog certifications

While Ai Chip Design Rtl focuses on creating the hardware description code for AI chips, Ai Chip Verification Engineer ensures that the RTL design functions correctly through rigorous testing. Both roles require knowledge of HDL languages and work closely within hardware development teams, but their core responsibilities differ—design versus verification.

What are popular job titles related to Ai Chip Design Rtl jobs in Portland, OR? For Ai Chip Design Rtl jobs in Portland, OR, the most frequently searched job titles are:
What job categories do people searching Ai Chip Design Rtl jobs in Portland, OR look for? The top searched job categories for Ai Chip Design Rtl jobs in Portland, OR are:
What cities near Portland, OR are hiring for Ai Chip Design Rtl jobs? Cities near Portland, OR with the most Ai Chip Design Rtl job openings:
Ai Chip Design Rtl jobs near you
Senior ASIC Design Engineer

Senior ASIC Design Engineer

ServerLogic

Beaverton, OR • On-site

Full-time

Posted 28 days ago

Job description

Sr/ ASIC Design Engineer
(5+ Years of Experience)
DESCRIPTION OF POSITION/DUTIES -
  1. Architect a block of an ASIC and write a microarchitecture specification (MAS) for the block
  2. Collaborate with other team members to integrate the block with the full chip
  3. Use Verilog to design and System Verilog for block level verification
  4. Assist the Verification team in reviewing and debugging test cases
  5. Run LINT and CDC checks on the RTL code and fix accordingly.
  6. Assist with synthesis and FPGA emulation.

QUALIFICATIONS -
  1. BA/MS degree and 5+ years of relevant work experience.
  2. Demonstrate knowledge of Verilog for chip design and verification.
  3. Must understand the ASIC flow from MAS to silicon including RTL design, verification, synthesis, timing constraints, GLS, FPGA prototyping, and first silicon bring up and debug.
  4. Understanding of digital design and verification practices.
  5. Be able to take a specification, write RTL and simulation vectors to verify their RTL.
  6. One prior RTL design is a requirement.
  7. Experience with USB 2.0, USB 3.2, USB4, or PCIe is desired.

Apply