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Freelance Asic Rtl Design Engineer Jobs in Portland, OR

Sr/ ASIC Design Engineer (5+ Years of Experience) DESCRIPTION OF POSITION/DUTIES - * Architect a ... Run LINT and CDC checks on the RTL code and fix accordingly. * Assist with synthesis and FPGA ...

Apple's Silicon Engineering team is looking for a highly skilled and motivated ASIC Design Engineer ... Develop RTL using SystemVerilog and perform synthesis. Verification: Engage with simulation-based ...

RTL Design Engineer

Beaverton, OR

$143.60K/yr

RTL Design Engineer At Apple, we work every day to craft products that enrich people's lives. If you're passionate about taking on unsolved challenges, we have a great opportunity for a results ...

RTL Design Engineer

Beaverton, OR · On-site

$141.50K/yr

If you're passionate about taking on unsolved challenges, we have a great opportunity for a results-oriented and highly motivated RTL Design Engineer. This is an exciting position in the world class ...

RTL Design Engineer

Beaverton, OR · On-site

$141.50K/yr

If you're passionate about taking on unsolved challenges, we have a great opportunity for a results-oriented and highly motivated RTL Design Engineer. This is an exciting position in the world class ...

If you're passionate about taking on unsolved challenges, we have a great opportunity for a results-oriented and highly motivated RTL Design Engineer. This is an exciting position in the world class ...

RTL Design Engineer

Hillsboro, OR

$105.65K - $200.34K/yr

Develops the logic design, register transfer level (RTL) coding, and simulation for a CPU required ... Silicon and Platform Engineering Group (SPE): Deliver breakthrough silicon and platform solutions ...

ASIC Design Engineer Imagine what you could do here. At Apple, new insights have a way of becoming ... Verilog RTL Logic Design experience. Preferred Qualifications * Experience writing specifications ...

As an ASIC Design Engineer, your responsibilities span various aspects of SOC design:- Write ... Verilog RTL Logic Design experience. Experience writing specifications and converting them to ...

As an ASIC Design Engineer, your responsibilities span various aspects of SOC design:- Write ... Verilog RTL Logic Design experience. Experience writing specifications and converting them to ...

As a CPU RTL Logic Design Engineer your responsibilities will include but are not limited to: Collaborates, drives and develops logic design, register transfer level (RTL) coding, and simulation for ...

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Freelance Asic Rtl Design Engineer information

See Portland, OR salary details

$15

$50

$140

How much do freelance asic rtl design engineer jobs pay per hour?

As of May 28, 2026, the average hourly pay for freelance asic rtl design engineer in Portland, OR is $50.59, according to ZipRecruiter salary data. Most workers in this role earn between $25.77 and $65.53 per hour, depending on experience, location, and employer.
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Senior ASIC Design Engineer

Senior ASIC Design Engineer

ServerLogic

Beaverton, OR • On-site

Full-time

Posted 28 days ago


Job description

Sr/ ASIC Design Engineer
(5+ Years of Experience)
DESCRIPTION OF POSITION/DUTIES -
  1. Architect a block of an ASIC and write a microarchitecture specification (MAS) for the block
  2. Collaborate with other team members to integrate the block with the full chip
  3. Use Verilog to design and System Verilog for block level verification
  4. Assist the Verification team in reviewing and debugging test cases
  5. Run LINT and CDC checks on the RTL code and fix accordingly.
  6. Assist with synthesis and FPGA emulation.

QUALIFICATIONS -
  1. BA/MS degree and 5+ years of relevant work experience.
  2. Demonstrate knowledge of Verilog for chip design and verification.
  3. Must understand the ASIC flow from MAS to silicon including RTL design, verification, synthesis, timing constraints, GLS, FPGA prototyping, and first silicon bring up and debug.
  4. Understanding of digital design and verification practices.
  5. Be able to take a specification, write RTL and simulation vectors to verify their RTL.
  6. One prior RTL design is a requirement.
  7. Experience with USB 2.0, USB 3.2, USB4, or PCIe is desired.