As a CPU RTL Logic Design Engineer your responsibilities will include but are not limited to: Collaborates, drives and develops logic design, register transfer level (RTL) coding, and simulation for ...
As a CPU RTL Logic Design Engineer your responsibilities will include but are not limited to: Collaborates, drives and develops logic design, register transfer level (RTL) coding, and simulation for ...
FE RTL Infrastructure - CAD Engineer
Beaverton, OR · On-site
$172K/yr
Description As a Front-End (FE) RTL Infrastructure - CAD Engineer, you will play a major role in developing and supporting a reliable infrastructure and work environments that design and verification ...
FE RTL Infrastructure - CAD Engineer
Beaverton, OR · On-site
$172K/yr
Description As a Front-End (FE) RTL Infrastructure - CAD Engineer, you will play a major role in developing and supporting a reliable infrastructure and work environments that design and verification ...
Principal Logic Design Engineer
Hillsboro, OR · On-site
$127K - $236K/yr
Own micro-architecture definition and RTL design for critical blocks such as schedulers, command ... ASIC synthesis, timing constraint, CDC/RDC experience * UVM Verification experience * Memory (HBM ...
Principal Logic Design Engineer
Hillsboro, OR · On-site
$127K - $236K/yr
Own micro-architecture definition and RTL design for critical blocks such as schedulers, command ... ASIC synthesis, timing constraint, CDC/RDC experience * UVM Verification experience * Memory (HBM ...
FE RTL Infrastructure - CAD Engineer
Beaverton, OR · On-site
$172K/yr
Description As a Front-End (FE) RTL Infrastructure - CAD Engineer, you will play a major role in developing and supporting a reliable infrastructure and work environments that design and verification ...
FE RTL Infrastructure - CAD Engineer
Beaverton, OR · On-site
$172K/yr
Description As a Front-End (FE) RTL Infrastructure - CAD Engineer, you will play a major role in developing and supporting a reliable infrastructure and work environments that design and verification ...
Principal Logic Design Engineer
Hillsboro, OR · On-site
$127K - $236K/yr
Own micro-architecture definition and RTL design for critical blocks such as schedulers, command ... ASIC synthesis, timing constraint, CDC/RDC experience * UVM Verification experience * Memory (HBM ...
Principal Logic Design Engineer
Hillsboro, OR · On-site
$127K - $236K/yr
Own micro-architecture definition and RTL design for critical blocks such as schedulers, command ... ASIC synthesis, timing constraint, CDC/RDC experience * UVM Verification experience * Memory (HBM ...
Principal Logic Design Engineer
Hillsboro, OR · Hybrid
$127K - $236K/yr
Own micro-architecture definition and RTL design for critical blocks such as schedulers, command ... ASIC synthesis, timing constraint, CDC/RDC experience * UVM Verification experience * Memory (HBM ...
Principal Logic Design Engineer
Hillsboro, OR · Hybrid
$127K - $236K/yr
Own micro-architecture definition and RTL design for critical blocks such as schedulers, command ... ASIC synthesis, timing constraint, CDC/RDC experience * UVM Verification experience * Memory (HBM ...
ASIC Design Engineer
Beaverton, OR · On-site
$150 - $210/hr
Description As an ASIC Design Engineer, your responsibilities span various aspects of SOC design ... Verilog RTL Logic Design experience. Preferred Qualifications * Experience writing specifications ...
ASIC Design Engineer
Beaverton, OR · On-site
$150 - $210/hr
Description As an ASIC Design Engineer, your responsibilities span various aspects of SOC design ... Verilog RTL Logic Design experience. Preferred Qualifications * Experience writing specifications ...
Principal Logic Design Engineer
Hillsboro, OR · Hybrid
$127K - $236K/yr
Own micro-architecture definition and RTL design for critical blocks such as schedulers, command ... ASIC synthesis, timing constraint, CDC/RDC experience * UVM Verification experience * Memory (HBM ...
Principal Logic Design Engineer
Hillsboro, OR · Hybrid
$127K - $236K/yr
Own micro-architecture definition and RTL design for critical blocks such as schedulers, command ... ASIC synthesis, timing constraint, CDC/RDC experience * UVM Verification experience * Memory (HBM ...
As a logic design engineer, you will be involved in all phases of the design, from concept study ... You will provide high-quality RTL description, including assertions, for the design. Use formal ...
As a logic design engineer, you will be involved in all phases of the design, from concept study ... You will provide high-quality RTL description, including assertions, for the design. Use formal ...
DDR Design Engineer
Beaverton, OR · On-site
As a logic design engineer, you will be involved in all phases of the design, from concept study ... You will provide high-quality RTL description, including assertions, for the design. Use formal ...
DDR Design Engineer
Beaverton, OR · On-site
As a logic design engineer, you will be involved in all phases of the design, from concept study ... You will provide high-quality RTL description, including assertions, for the design. Use formal ...
As a logic design engineer, you will be involved in all phases of the design, from concept study ... You will provide high-quality RTL description, including assertions, for the design. Use formal ...
As a logic design engineer, you will be involved in all phases of the design, from concept study ... You will provide high-quality RTL description, including assertions, for the design. Use formal ...
Hardware Design Engineer
Hillsboro, OR · Hybrid
$106K - $198K/yr
RTL coding and verification * Memory Controller + PHY integration and verification * Customer ... Significant ASIC and/or FPGA design experience * Ability to learn quickly and work independently
Hardware Design Engineer
Hillsboro, OR · Hybrid
$106K - $198K/yr
RTL coding and verification * Memory Controller + PHY integration and verification * Customer ... Significant ASIC and/or FPGA design experience * Ability to learn quickly and work independently
Hardware Design Engineer
Hillsboro, OR · Hybrid
$106K - $198K/yr
RTL coding and verification * Memory Controller + PHY integration and verification * Customer ... Significant ASIC and/or FPGA design experience * Ability to learn quickly and work independently
Hardware Design Engineer
Hillsboro, OR · Hybrid
$106K - $198K/yr
RTL coding and verification * Memory Controller + PHY integration and verification * Customer ... Significant ASIC and/or FPGA design experience * Ability to learn quickly and work independently
Hardware Design Engineer
Hillsboro, OR · On-site
$106K - $198K/yr
RTL coding and verification * Memory Controller + PHY integration and verification * Customer ... Significant ASIC and/or FPGA design experience * Ability to learn quickly and work independently
Hardware Design Engineer
Hillsboro, OR · On-site
$106K - $198K/yr
RTL coding and verification * Memory Controller + PHY integration and verification * Customer ... Significant ASIC and/or FPGA design experience * Ability to learn quickly and work independently
DDR Design Engineer
Beaverton, OR · On-site
As a logic design engineer, you will be involved in all phases of the design, from concept study ... You will provide high-quality RTL description, including assertions, for the design. Use formal ...
DDR Design Engineer
Beaverton, OR · On-site
As a logic design engineer, you will be involved in all phases of the design, from concept study ... You will provide high-quality RTL description, including assertions, for the design. Use formal ...
FE RTL Infrastructure - CAD Engineer
$150K - $277K/yr
Description As a Front-End (FE) RTL Infrastructure - CAD Engineer, you will play a major role in developing and supporting a reliable infrastructure and work environments that design and verification ...
FE RTL Infrastructure - CAD Engineer
$150K - $277K/yr
Description As a Front-End (FE) RTL Infrastructure - CAD Engineer, you will play a major role in developing and supporting a reliable infrastructure and work environments that design and verification ...
FE RTL Infrastructure - CAD Engineer
$129K - $194K/yr
Description As a Front-End (FE) RTL Infrastructure - CAD Engineer, you will play a major role in developing and supporting a reliable infrastructure and work environments that design and verification ...
FE RTL Infrastructure - CAD Engineer
$129K - $194K/yr
Description As a Front-End (FE) RTL Infrastructure - CAD Engineer, you will play a major role in developing and supporting a reliable infrastructure and work environments that design and verification ...
FE RTL Infrastructure - CAD Engineer
$129K - $194K/yr
Description As a Front-End (FE) RTL Infrastructure - CAD Engineer, you will play a major role in developing and supporting a reliable infrastructure and work environments that design and verification ...
FE RTL Infrastructure - CAD Engineer
$129K - $194K/yr
Description As a Front-End (FE) RTL Infrastructure - CAD Engineer, you will play a major role in developing and supporting a reliable infrastructure and work environments that design and verification ...
FE RTL Infrastructure - CAD Engineer
$150K - $277K/yr
Description As a Front-End (FE) RTL Infrastructure - CAD Engineer, you will play a major role in developing and supporting a reliable infrastructure and work environments that design and verification ...
FE RTL Infrastructure - CAD Engineer
$150K - $277K/yr
Description As a Front-End (FE) RTL Infrastructure - CAD Engineer, you will play a major role in developing and supporting a reliable infrastructure and work environments that design and verification ...
RTL coding: Verilog / System Verilog * Master's degree or PHD in Electrical Engineering, Computer Engineering or equivalent. * 5+ years of experience with RTL Design * Good English skills ...
RTL coding: Verilog / System Verilog * Master's degree or PHD in Electrical Engineering, Computer Engineering or equivalent. * 5+ years of experience with RTL Design * Good English skills ...
Freelance Asic Rtl Design Engineer information
See Portland, OR salary details
$24.95 is the 25th percentile. Wages below this are outliers.
$15.81 - $27.12
31% of jobs
The median wage is $34.09 / hr.
$27.12 - $38.42
31% of jobs
$38.42 - $49.73
4% of jobs
$59.63 is the 75th percentile. Wages above this are outliers.
$49.73 - $61.04
10% of jobs
$61.04 - $72.35
9% of jobs
$72.35 - $83.66
5% of jobs
$83.66 - $94.97
0% of jobs
$94.97 - $106.28
8% of jobs
$106.28 - $117.59
0% of jobs
$117.59 - $128.90
0% of jobs
$128.90 - $140.21
1% of jobs
$15
$50
$140
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Full-time
Medical, Retirement, PTO
Re-posted 10 days ago
Intel rating
8.7
Based on 147 frontline employees who took The Breakroom Quiz
19th of 157 rated electronics manufacturers
Job description
Intel is shaping the future of technology to help create a better future for the entire world. Our work in pushing forward fields like AI, analytics, and cloud-to-edge technology is at the heart of countless innovations. With a career at Intel, you'll have the opportunity to use technology to power major breakthroughs and create enhancements that improve our everyday quality of life. Join us and help make the future more wonderful for everyone.
Life at Intel
We developed the Intel microprocessors, a foundational technology that powers a diverse range of devices-from entry-level PCs to high-end gaming desktops and laptops, as well as data center solutions and many other applications. As part of our team, you will help design the next generation of high-performance microprocessors. We are looking for a skilled individual who is hands-on with RTL implementation for integer, floating point and reservation station logic and can provide technical leadership to deliver world-class products.
As a CPU RTL Logic Design Engineer your responsibilities will include but are not limited to:
Collaborates, drives and develops logic design, register transfer level (RTL) coding, and simulation for a CPU required to generate cell libraries, functional units, and the CPU IP block for integration in full chip designs.
Participates actively in the definition of architecture and microarchitecture features of the CPU being designed.
Applies various strategies, tools, and methods to write RTL and optimize logic to qualify the design to meet power, performance, area, and timing goals as well as design integrity for physical implementation.
Reviews the verification plan and implementation to ensure design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features.
Technical Guidance: Provide technical leadership and support to the design team leadership including proposing creative, innovative methodology and process initiatives to consistently improve efficiency and quality.
Cross team collaboration: Work closely with architecture and backend teams and with other design teams towards achieving best-in-class products.
Build a strong and technically vital organization. Cultivate and reinforce appropriate group values, norms and behaviors.
Behavioral traits that we are looking for:
Excellent in problem-solving, analytical
Excellent written and verbal communication skills
Ability to work effectively in a fast-paced environment and collaborative environment
You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
Minimum Qualifications:
Education Requirement
Bachelor's degree in Computer Science, Electrical, Electronics, Engineering, or related field with 12+ years of work experience OR
Master's degree in Computer Science, Electrical, Electronics, Engineering, or related field with 10+ years of work experience OR
PhD in Computer Science, Electrical, Electronics, Engineering, or related field with 6+ years of work experience.
Minimum Required Qualifications:
6+ years of experience in silicon development in CPU microarchitecture and logic design.
5+ years of experience in technical leadership including delivering successful IP Projects.
6+ years of experience with Timing Closure, Power Convergence; integer and/or floating point, OOO execution, reservation station design
Additional Preferred Qualifications:
Experience on x86 CPU microarchitecture
. Experience with driving front end methodologies and championing the use of automation / AI tools to realize tangible benefits visible at the product level.
Experience would be obtained through a combination of prior education level classes, and current level school classes, projects, research, and relevant previous job and/or internship experience.
Benefits at Intel
Our total rewards package goes above and beyond just a paycheck. Whether you're looking to build your career, improve your health, or protect your wealth, we offer generous benefits to help you achieve your goals. Go to Intel Benefits ' Intel Careers for details of benefits available to you. Intel reserves the right to modify, change or discontinue benefit plans at any time in its sole discretion.
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.
Annual Salary Range for jobs which could be performed in the US: $164,470.00-311,890.00 USDThe range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.Work Model for this Role
This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.*
ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.About Intel
Sourced by ZipRecruiter
Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore's Law to bring smart, connected devices to every person on Earth
Industry
Manufacturing
Company size
10,000+ Employees
Headquarters location
Santa Clara, CA, US
Year founded
1968