1

Freelance Asic Rtl Design Engineer Jobs in Portland, OR

Principal Logic Design Engineer

Hillsboro, OR · Hybrid

$127.40K - $236.60K/yr

Own micro-architecture definition and RTL design for critical blocks such as schedulers, command ... ASIC synthesis, timing constraint, CDC/RDC experience * UVM Verification experience * Memory (HBM ...

New

Principal Logic Design Engineer

Hillsboro, OR · Hybrid

$127.40K - $236.60K/yr

Own micro-architecture definition and RTL design for critical blocks such as schedulers, command ... ASIC synthesis, timing constraint, CDC/RDC experience * UVM Verification experience * Memory (HBM ...

New

Principal Logic Design Engineer

Hillsboro, OR · Hybrid

$127.40K - $236.60K/yr

Own micro-architecture definition and RTL design for critical blocks such as schedulers, command ... ASIC synthesis, timing constraint, CDC/RDC experience * UVM Verification experience * Memory (HBM ...

New

Principal Logic Design Engineer

Hillsboro, OR · Hybrid

$127.40K - $236.60K/yr

Own micro-architecture definition and RTL design for critical blocks such as schedulers, command ... ASIC synthesis, timing constraint, CDC/RDC experience * UVM Verification experience * Memory (HBM ...

New

As a logic design engineer, you will be involved in all phases of the design, from concept study ... You will provide high-quality RTL description, including assertions, for the design. Use formal ...

As a logic design engineer, you will be involved in all phases of the design, from concept study ... You will provide high-quality RTL description, including assertions, for the design. Use formal ...

Hardware Design Engineer

Hillsboro, OR · Hybrid

$106.90K - $198.50K/yr

RTL coding and verification * Memory Controller + PHY integration and verification * Customer ... Significant ASIC and/or FPGA design experience * Ability to learn quickly and work independently

As a logic design engineer, you will be involved in all phases of the design, from concept study ... You will provide high-quality RTL description, including assertions, for the design. Use formal ...

As a logic design engineer, you will be involved in all phases of the design, from concept study ... You will provide high-quality RTL description, including assertions, for the design. Use formal ...

Hardware Design Engineer

Hillsboro, OR · Hybrid

$106.90K - $198.50K/yr

RTL coding and verification * Memory Controller + PHY integration and verification * Customer ... Significant ASIC and/or FPGA design experience * Ability to learn quickly and work independently

Hardware Design Engineer

Hillsboro, OR · On-site

$106.90K - $198.50K/yr

RTL coding and verification * Memory Controller + PHY integration and verification * Customer ... Significant ASIC and/or FPGA design experience * Ability to learn quickly and work independently

Description As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC ... You will closely interact with RTL designer to understand design intent and clock structure, with ...

As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC design in terms ... You will closely interact with RTL designer to understand design intent and clock structure, with ...

As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC design in terms ... You will closely interact with RTL designer to understand design intent and clock structure, with ...

Description As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC ... You will closely interact with RTL designer to understand design intent and clock structure, with ...

next page

Showing results 1-20

Freelance Asic Rtl Design Engineer information

See Portland, OR salary details

$15

$50

$140

How much do freelance asic rtl design engineer jobs pay per hour?

As of May 28, 2026, the average hourly pay for freelance asic rtl design engineer in Portland, OR is $50.59, according to ZipRecruiter salary data. Most workers in this role earn between $25.77 and $65.53 per hour, depending on experience, location, and employer.
What are the most commonly searched types of Asic Rtl Design Engineer jobs in Portland, OR? The most popular types of Asic Rtl Design Engineer jobs in Portland, OR are:
What are popular job titles related to Freelance Asic Rtl Design Engineer jobs in Portland, OR? For Freelance Asic Rtl Design Engineer jobs in Portland, OR, the most frequently searched job titles are:
What job categories do people searching Freelance Asic Rtl Design Engineer jobs in Portland, OR look for? The top searched job categories for Freelance Asic Rtl Design Engineer jobs in Portland, OR are:
What cities near Portland, OR are hiring for Freelance Asic Rtl Design Engineer jobs? Cities near Portland, OR with the most Freelance Asic Rtl Design Engineer job openings:
Principal Logic Design Engineer

Principal Logic Design Engineer

Rambus

Hillsboro, OR • Hybrid

$127.40K - $236.60K/yr

Other

Medical, Dental, Retirement

Posted 2 days ago


Job description

Overview

Rambus, a premier chip and silicon IP provider, is seeking to hire an exceptional Principal Logic Design Engineer to join our Silicon IP (SIP) team in Hillsboro, Oregon. Candidates will be joining some of the brightest inventors and engineers in the world to develop products that make data faster and safer. 

In this role, the candidate will be reporting to the Director of Engineering as an individual contributor. As a Principal Logic Design Engineer, you will play a pivotal role in the micro-architecture and design of our next- generation high performance and cutting-edge memory controllers for data centers and AI applications. This is a fast-growing market with high demand from tier-1 customers which gives ample opportunity for innovation and differentiation. If you like challenges and want to make a technical difference in the memory landscape during these exciting times in the semiconductor industry, this is the right opportunity for you. 

Rambus offers a flexible work environment, embracing a hybrid approach for most office-based roles. Employees are encouraged to spend an average of at least three days per week onsite, allowing for two days of remote work. 

Responsibilities
  • Own micro-architecture definition and RTL design for critical blocks such as schedulers, command pipelines, coherency/ordering logic and system interfaces 
  • Analyze performance, power, and area (PPA) trade-offs and drive design decisions based on quantitative data 
  • Collaborate closely with verification team to shape test plans and improve verification coverage 
  • Work with physical design team to understand and resolve timing, power, and congestion challenges 
  • Work with verification team on regression failure debug and root cause, and provide RTL fix if necessary 
  • Provide technical support to FAE team on pre-sales customer engagements 
  • Provide technical support to AE team on post-sales customer deliveries 
Qualifications
  • Strong System Verilog/Verilog RTL design expertise 
  • Questa/Incisive/VCS simulator experience 
  • Python/Perl/TCL scripting experience 
  • Ability to learn quickly and work independently 
  • Solid communication and project management skills 
  • 10+ years of logic design experience (ASIC/FPGA) with BSEE, or  
  • 8+ years of logic design experience (ASIC/FPGA) with MSEE 

Definite Plus: 

  • ASIC synthesis, timing constraint, CDC/RDC experience 
  • UVM Verification experience 
  • Memory (HBM, LPDDR) expertise 
  • AMBA AXI or CHI design experience 

About Rambus 

Rambus is a global company that makes industry-leading memory interface chips and Silicon IP to advance data center connectivity and solve the bottleneck between memory and processing. With over 30 years of semiconductor experience, we are a leading provider of high-performance products and innovations that maximize the bandwidth, capacity and security for AI and other data-intensive workloads. Our world-class team is the foundation of our company, and our innovative spirit drives us to develop the cutting-edge products and technologies essential for tomorrow's systems.  

Rambus offers a competitive compensation package including base salary, bonus, equity, matching 401(k), employee stock purchase plan, comprehensive medical and dental benefits, time-off program, and gym membership.  

The US salary range for this full-time position is $127,400 to $236,600. Our salary ranges are determined by role, level and location. The successful candidate's starting pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. 

At Rambus, we are committed to fostering a workplace where every individual is respected, supported, and empowered to succeed. We value a range of perspectives and experiences that contribute to innovation and collaboration. Our goal is to ensure that all team members have equitable access to opportunities, resources, and a sense of belonging. We believe that a culture of fairness and inclusion helps us all do our best work. 

 Rambus is proud to be an Equal Employment Opportunity and Affirmative Action employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender identity, gender expression, age, status as a protected veteran, status as an individual with a disability, genetic information, or other applicable legally protected characteristics.  

Rambus is committed to providing reasonable accommodations for qualified individuals with disabilities and disabled veterans during our job application procedures. If you require assistance or an accommodation due to a disability, please feel free to inform us in your application. 

Rambus does not accept unsolicited resumes from headhunters, recruitment agencies or fee-based recruitment services. 

For more information about Rambus, visit rambus.com. For additional information on life at Rambus and our current openings, check outrambus.com/careers/. 

#LI-HYBRID

#LI-RF1

Employment Type: OTHER