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Asic Rtl Design Engineer Jobs (NOW HIRING)

Cybercoders

Sr. ASIC RTL Design Engineer

Irvine, CA · On-site

$150K - $250K/yr

Sr. ASIC RTL Design Engineer Job Title: Sr. ASIC RTL Design Engineer Job Location: San Jose, CA or Irvine, CA Compensation: $150K - $250K base DOE plus equity Requirements: Logic Design, RTL ...

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Qualcomm

Processor ASIC RTL Design Engineer

San Diego, CA · On-site

$127K - $190K/yr

Engineering Group, Engineering Group > DSP Architecture and Design General Summary: A variety of ... This position involves in-depth understanding of the ASIC design flow from RTL to GDS2 and the ...

CYNET SYSTEMS

ASIC/RTL Design Engineer 2

San Jose, CA · On-site

$60 - $62/hr

Hands-on experience in industry ASIC design flow including RTL coding, debugging/verification, and supporting synthesis and timing closure. * Working knowledge of Client cores and other I/O standard ...

ServerLogic

Senior ASIC Design Engineer

Beaverton, OR · On-site

Sr/ ASIC Design Engineer (5+ Years of Experience) DESCRIPTION OF POSITION/DUTIES - * Architect a ... Run LINT and CDC checks on the RTL code and fix accordingly. * Assist with synthesis and FPGA ...

TetraMem INC

ASIC RTL/SoC Design Engineer

Fremont, CA · On-site

Lead RTL design, simulation, and verification efforts for TetraMem ASIC/SoC products, ensuring ... Play a mentorship role by guiding and coaching junior engineers, sharing expertise and best ...

Normal Computing

RTL Design Engineer

New York, NY · On-site

$205K - $285K/yr

The Role As an RTL Design Engineer at Normal, you will design and verify the digital logic at the ... This work sits at the intersection of classical ASIC design, novel computing architectures, and a ...

TetraMem INC

ASIC RTL/SoC Design Engineer

Fremont, CA · On-site

Lead RTL design, simulation, and verification efforts for TetraMem ASIC/SoC products, ensuring ... Play a mentorship role by guiding and coaching junior engineers, sharing expertise and best ...

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Asic Rtl Design Engineer information

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How much do asic rtl design engineer jobs pay per year?

As of Jul 8, 2026, the average yearly pay for asic rtl design engineer in the United States is $150,195.00, according to ZipRecruiter salary data. Most workers in this role earn between $131,500.00 and $180,000.00 per year, depending on experience, location, and employer.

What is an ASIC RTL Design Engineer job?

An ASIC RTL Design Engineer is responsible for designing and implementing the digital logic of Application-Specific Integrated Circuits (ASICs) using Hardware Description Languages (HDLs) like Verilog or VHDL. They translate system-level specifications into Register Transfer Level (RTL) code, ensuring functionality, performance, and power efficiency. Their role also involves simulation, synthesis, timing analysis, and debugging to verify and optimize the design. They collaborate with verification, physical design, and firmware teams to ensure seamless integration.

What are the typical daily responsibilities of an ASIC RTL Design Engineer?

As an ASIC RTL Design Engineer, your daily responsibilities often include designing and verifying Register Transfer Level (RTL) code for specific chip modules, running simulations, and debugging functional issues. You will frequently collaborate with verification engineers, physical design teams, and system architects to ensure the design meets specifications and performance goals. The role also involves attending regular team meetings to coordinate project tasks and document progress. Staying current with evolving industry methodologies and engaging in code reviews are also part of the typical workflow.

What are the key skills and qualifications needed to thrive in the Asic Rtl Design Engineer position, and why are they important?

To thrive as an ASIC RTL Design Engineer, you need a strong background in digital logic design, Verilog or VHDL coding, and a relevant degree in electrical or computer engineering. Proficiency with industry-standard EDA tools such as Synopsys, Cadence, and ModelSim, as well as familiarity with simulation and synthesis processes, is typically required. Attention to detail, strong problem-solving abilities, and effective communication skills are highly valued in this position. These competencies are essential to ensuring robust, efficient, and collaborative chip development within project timelines.

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Infographic showing various Asic Rtl Design Engineer job openings in the United States as of July 2026, with employment types broken down into 95% Full Time, 1% Part Time, 2% Contract, and 2% Summer. Highlights an 89% Physical, 6% Hybrid, and 5% Remote job distribution, with an average salary of $150,195 per year, or $72.2 per hour.
Sr. ASIC RTL Design Engineer

Sr. ASIC RTL Design Engineer

Cybercoders

Irvine, CA • On-site

$150K - $250K/yr

Full-time

Medical, Dental, Vision, Life, Retirement, PTO

This job post has expired today. Applications are no longer accepted.

Job description

Sr. ASIC RTL Design Engineer

Job Title: Sr. ASIC RTL Design Engineer
Job Location: San Jose, CA or Irvine, CA
Compensation: $150K - $250K base DOE plus equity
Requirements: Logic Design, RTL, Processor Architecture, Memory, Cache Subsystems, NoC, Interconnects
Position Overview
We are seeking a highly skilled Sr. ASIC RTL Design Engineer to join our innovative team. The ideal candidate will be responsible for designing and implementing complex ASIC designs, focusing on RTL development and ensuring high performance and efficiency in our next-generation products.
Key Responsibilities

  • Design and develop RTL for complex ASIC designs
  • Collaborate with cross-functional teams to define specifications and architecture
  • Perform logic design and data path design for various components
  • Optimize designs for performance, area, and power consumption
  • Conduct simulations and validations to ensure design functionality
  • Participate in design reviews and provide constructive feedback
  • Support the integration of memory and cache subsystems within the architecture
  • Work on interconnect architectures, including NOC solutions
  • Implement and verify floating-point arithmetic operations in design
  • Stay updated with industry trends and advancements in RISC-V architecture.

Qualifications

  • Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field
  • 5+ years of experience in ASIC design and RTL development
  • Strong knowledge of logic design and RTL design methodologies
  • Experience with processor architecture and system design
  • Familiarity with memory and cache subsystems
  • Proficiency in interconnect design, including NOC
  • Hands-on experience with RISC-V architecture is a plus
  • Solid understanding of floating-point arithmetic and data path design is a plus

Benefits

  • Vacation/PTO
  • Equity
  • Medical
  • Dental
  • Vision
  • Life Insurance
  • 401k
- For this position, you must be currently authorized to work in the United States without the need for sponsorship for a non-immigrant visa. CyberCoders will consider for Employment in the City of Los Angeles qualified Applicants with Criminal Histories in a manner consistent with the requirements of the Los Angeles Fair Chance Initiative for Hiring (Ban the Box) Ordinance.This job was first posted by CyberCoders on 07/08/2026 and applications will be accepted on an ongoing basis until the position is filled or closed.Everforth CyberCoders is proud to be an Equal Opportunity Employer
All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, age, sexual orientation, gender identity or expression, national origin, ancestry, citizenship, genetic information, registered domestic partner status, marital status, status as a crime victim, disability, protected veteran status, or any other characteristic protected by law. Our hiring process includes AI screening for keywords and minimum qualifications, and a virtual recruiter as part of the application process. A human recruiter reviews all results. Click here for details on our virtual recruiter .  Everforth CyberCoders will consider qualified applicants with criminal histories in a manner consistent with the requirements of applicable state and local law, including but not limited to the Los Angeles County Fair Chance Ordinance, the San Francisco Fair Chance Ordinance, and the California Fair Chance Act. Everforth CyberCoders is committed to working with and providing reasonable accommodation to individuals with physical and mental disabilities. Individuals needing special assistance or an accommodation while seeking employment can contact a member of our Human Resources team at Benefits@CyberCoders.com to make arrangements.
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About CyberCoders

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CyberCoders is a cutting-edge recruiting firm headquartered in Irvine, CA, US. The company operates within the technology industry, specializing in connecting talented professionals with suitable positions across a variety of sectors. Offering a broad spectrum of services, CyberCoders uses innovative, data-driven strategies and a proprietary matching technology to pair candidates with suitable job openings. Since its inception in 1999, CyberCoders has distinguished itself as an industry trailblazer. The company's mission is to deliver effective talent solutions, thus enabling both businesses and workers to achieve their goals.

Industry

Technology, communication and media

Company size

51 - 200 Employees

Headquarters location

Irvine, CA, US

Year founded

1999

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