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Asic Rtl Design Engineer Jobs (NOW HIRING)

Infoyogi LLC

ASIC/RTL Design Engineer

San Jose, CA · On-site

ASIC/RTL Design Engineer Location: San Jose, CA Duration : 12 months plus JOB DUTIES: The work will expose the designer to a number of IP including ARM cores, Ethernet, DDR, DMA, PCIE, SATA ...

VIVA USA INC

ASIC RTL Design Engineer

San Jose, CA · On-site

Our RTL Design Engineers are expected contribute in all aspects of SoC design including: Chip ... SoC Architecture; knowledge and hand-on experience from industry ASIC design flow including RTL ...

Qualcomm

Processor ASIC RTL Design Engineer

San Diego, CA · On-site

$127K - $190K/yr

Engineering Group, Engineering Group > DSP Architecture and Design General Summary: A variety of ... This position involves in-depth understanding of the ASIC design flow from RTL to GDS2 and the ...

CYNET SYSTEMS

ASIC/RTL Design Engineer 2

San Jose, CA · On-site

$60 - $62/hr

Hands-on experience in industry ASIC design flow including RTL coding, debugging/verification, and supporting synthesis and timing closure. * Working knowledge of Client cores and other I/O standard ...

Dexian

ASIC/SoC RTL Design Engineer

Campbell, CA · On-site

$60 - $62.50/hr

SoC RTL Design Engineer San Jose, CA: 100% Onsite 6 + Months $60-$62.50/HR Role: Design and develop ... Experience in ASIC/SoC design and RTL coding Knowledge of ARM and standard I/O interfaces Dexian ...

Dexian DISYS

ASIC/SoC RTL Design Engineer

San Jose, CA · On-site

$60 - $62.50/hr

SoC RTL Design Engineer San Jose, CA: 100% Onsite 6 + Months $60-$62.50/HR Role: Design and develop ... Experience in ASIC/SoC design and RTL coding Knowledge of ARM and standard I/O interfaces Dexian ...

ServerLogic

Senior ASIC Design Engineer

Beaverton, OR · On-site

Sr/ ASIC Design Engineer (5+ Years of Experience) DESCRIPTION OF POSITION/DUTIES - * Architect a ... Run LINT and CDC checks on the RTL code and fix accordingly. * Assist with synthesis and FPGA ...

TetraMem INC

ASIC RTL/SoC Design Engineer

Fremont, CA · On-site

Lead RTL design, simulation, and verification efforts for TetraMem ASIC/SoC products, ensuring ... Play a mentorship role by guiding and coaching junior engineers, sharing expertise and best ...

TetraMem INC

ASIC RTL/SoC Design Engineer

Fremont, CA · On-site

Lead RTL design, simulation, and verification efforts for TetraMem ASIC/SoC products, ensuring ... Play a mentorship role by guiding and coaching junior engineers, sharing expertise and best ...

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How much do asic rtl design engineer jobs pay per year?

As of Jun 18, 2026, the average yearly pay for asic rtl design engineer in the United States is $150,195.00, according to ZipRecruiter salary data. Most workers in this role earn between $131,500.00 and $180,000.00 per year, depending on experience, location, and employer.

What is an ASIC RTL Design Engineer job?

An ASIC RTL Design Engineer is responsible for designing and implementing the digital logic of Application-Specific Integrated Circuits (ASICs) using Hardware Description Languages (HDLs) like Verilog or VHDL. They translate system-level specifications into Register Transfer Level (RTL) code, ensuring functionality, performance, and power efficiency. Their role also involves simulation, synthesis, timing analysis, and debugging to verify and optimize the design. They collaborate with verification, physical design, and firmware teams to ensure seamless integration.

What are the typical daily responsibilities of an ASIC RTL Design Engineer?

As an ASIC RTL Design Engineer, your daily responsibilities often include designing and verifying Register Transfer Level (RTL) code for specific chip modules, running simulations, and debugging functional issues. You will frequently collaborate with verification engineers, physical design teams, and system architects to ensure the design meets specifications and performance goals. The role also involves attending regular team meetings to coordinate project tasks and document progress. Staying current with evolving industry methodologies and engaging in code reviews are also part of the typical workflow.

What are the key skills and qualifications needed to thrive in the Asic Rtl Design Engineer position, and why are they important?

To thrive as an ASIC RTL Design Engineer, you need a strong background in digital logic design, Verilog or VHDL coding, and a relevant degree in electrical or computer engineering. Proficiency with industry-standard EDA tools such as Synopsys, Cadence, and ModelSim, as well as familiarity with simulation and synthesis processes, is typically required. Attention to detail, strong problem-solving abilities, and effective communication skills are highly valued in this position. These competencies are essential to ensuring robust, efficient, and collaborative chip development within project timelines.

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Asic Rtl Design Engineer jobs near you
Infographic showing various Asic Rtl Design Engineer job openings in the United States as of June 2026, with employment types broken down into 79% Full Time, 18% Part Time, and 3% Contract. Highlights an 87% Physical, 5% Hybrid, and 8% Remote job distribution, with an average salary of $150,195 per year, or $72.2 per hour.
ASIC/RTL Design Engineer

ASIC/RTL Design Engineer

Infoyogi LLC

San Jose, CA • On-site

Other

Posted 15 days ago

Job description

ASIC/RTL Design Engineer

Location: San Jose, CA

Duration : 12 months plus

JOB DUTIES:

The work will expose the designer to a number of IP including ARM cores, Ethernet, DDR, DMA, PCIE, SATA

Successful candidates will be responsible for leading, and participating in, the design of leading edge SoCs in advanced digital CMOS processes. Our RTL Design Engineers are expected contribute in all aspects of SoC design including: Chip definition, Architecture development and modeling, Development of micro-architectural specifications, Conversion of micro-architectural specifications to logic implementation, Verification, emulation, debug, synthesis, and timing closure, Interfacing with physical execution, software, and silicon bring-up teams.

EXPERIENCE AND EDUCATION:

SoC Architecture; knowledge and hand-on experience from industry ASIC design flow including RTL coding, debugging/verification, and supporting synthesis and timing closure. Working knowledge of ARM cores and other I/O standard interfaces. An ideal candidate would also exhibit: Strong communication and documentation skills, Good organizational, time management and multitasking skills, Strong initiative and discipline to follow-through, Technical leadership

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