ASIC/RTL Design Engineer
San Jose, CA · On-site
Our RTL Design Engineers are expected contribute in all aspects of SoC design including: Chip ... SoC Architecture; knowledge and hand-on experience from industry ASIC design flow including RTL ...
New
ASIC/RTL Design Engineer
San Jose, CA · On-site
Our RTL Design Engineers are expected contribute in all aspects of SoC design including: Chip ... SoC Architecture; knowledge and hand-on experience from industry ASIC design flow including RTL ...
New
RTL Engineer - Networking ASIC Saratoga, CA Full-Time Join an innovative hardware company building ... Design packet buffering, queuing, and scheduling microarchitecture * Implement high-speed ...
RTL Engineer - Networking ASIC Saratoga, CA Full-Time Join an innovative hardware company building ... Design packet buffering, queuing, and scheduling microarchitecture * Implement high-speed ...
ASIC/RTL Design Engineer 5
San Jose, CA · On-site
$82 - $86/hr
Medical
Dental
Vision
Life
Retirement
Hands-on experience with industry ASIC design flow including RTL coding, debugging/verification ... We deliver agile, scalable talent solutions across IT, engineering, life sciences, clinical, and ...
New
Quick apply
ASIC/RTL Design Engineer 5
San Jose, CA · On-site
$82 - $86/hr
Medical
Dental
Vision
Life
Retirement
Hands-on experience with industry ASIC design flow including RTL coding, debugging/verification ... We deliver agile, scalable talent solutions across IT, engineering, life sciences, clinical, and ...
New
ASIC/SoC RTL Design Engineer Location: Palo Alto, CA (Or potentially Burlington, MA) Length of Contract: 6 months+ (Temp-to-Perm) Ideal Start: 6/1/2026 Responsibilities : Own end-to-end design of ...
ASIC/SoC RTL Design Engineer Location: Palo Alto, CA (Or potentially Burlington, MA) Length of Contract: 6 months+ (Temp-to-Perm) Ideal Start: 6/1/2026 Responsibilities : Own end-to-end design of ...
ASIC/RTL Design Engineer 2
San Jose, CA · On-site
$60 - $62/hr
Hands-on experience in industry ASIC design flow including RTL coding, debugging/verification, and supporting synthesis and timing closure. * Working knowledge of Client cores and other I/O standard ...
Quick apply
ASIC/RTL Design Engineer 2
San Jose, CA · On-site
$60 - $62/hr
Hands-on experience in industry ASIC design flow including RTL coding, debugging/verification, and supporting synthesis and timing closure. * Working knowledge of Client cores and other I/O standard ...
ASIC/RTL Design Engineer Primary Skills : RTL coding, TCL coding, Python coding, understanding of different CAD tools (synthesis, lint, CDC, RDC, PrimeTime). Location: San Jose CA Duration : 12 ...
ASIC/RTL Design Engineer Primary Skills : RTL coding, TCL coding, Python coding, understanding of different CAD tools (synthesis, lint, CDC, RDC, PrimeTime). Location: San Jose CA Duration : 12 ...
ASIC RTL/SoC Design Engineer
Fremont, CA · On-site
Medical
Retirement
PTO
Lead RTL design, simulation, and verification efforts for TetraMem ASIC/SoC products, ensuring ... Play a mentorship role by guiding and coaching junior engineers, sharing expertise and best ...
ASIC RTL/SoC Design Engineer
Fremont, CA · On-site
Medical
Retirement
PTO
Lead RTL design, simulation, and verification efforts for TetraMem ASIC/SoC products, ensuring ... Play a mentorship role by guiding and coaching junior engineers, sharing expertise and best ...
As a Senior ASIC Design Engineer, you will own the complete RTL design lifecycle from micro-architecture specification through production silicon, working on complex IP design. THE PERSON: The ideal ...
As a Senior ASIC Design Engineer, you will own the complete RTL design lifecycle from micro-architecture specification through production silicon, working on complex IP design. THE PERSON: The ideal ...
ASIC RTL/SoC Design Engineer
Medical
Retirement
PTO
Lead RTL design, simulation, and verification efforts for TetraMem ASIC/SoC products, ensuring ... Play a mentorship role by guiding and coaching junior engineers, sharing expertise and best ...
ASIC RTL/SoC Design Engineer
Medical
Retirement
PTO
Lead RTL design, simulation, and verification efforts for TetraMem ASIC/SoC products, ensuring ... Play a mentorship role by guiding and coaching junior engineers, sharing expertise and best ...
Integration RTL Design Engineer
San Jose, CA · On-site
$145K/yr
As a Senior ASIC Design Engineer, you will own the complete RTL design lifecycle from micro-architecture specification through production silicon, working on complex IP design. THE PERSON: The ideal ...
Integration RTL Design Engineer
San Jose, CA · On-site
$145K/yr
As a Senior ASIC Design Engineer, you will own the complete RTL design lifecycle from micro-architecture specification through production silicon, working on complex IP design. THE PERSON: The ideal ...
ASIC RTL/SoC Design Engineer
$110K - $300K/yr
Lead RTL design, simulation, and verification efforts for TetraMem ASIC/SoC products, ensuring ... Play a mentorship role by guiding and coaching junior engineers, sharing expertise and best ...
ASIC RTL/SoC Design Engineer
$110K - $300K/yr
Lead RTL design, simulation, and verification efforts for TetraMem ASIC/SoC products, ensuring ... Play a mentorship role by guiding and coaching junior engineers, sharing expertise and best ...
RTL Design Engineer Building AI chips that are hard-coded for individual model architectures. RTL ... both our existing and upcoming ASIC designs. In this role, you will work closely with ...
Quick apply
RTL Design Engineer Building AI chips that are hard-coded for individual model architectures. RTL ... both our existing and upcoming ASIC designs. In this role, you will work closely with ...
... RTL designs - Working with design verification and formal verification teams to verify ... front-end ASIC RTL design Tight-knit collaboration skills with excellent written and verbal ...
... RTL designs - Working with design verification and formal verification teams to verify ... front-end ASIC RTL design Tight-knit collaboration skills with excellent written and verbal ...
... RTL designs - Working with design verification and formal verification teams to verify ... front-end ASIC RTL design Tight-knit collaboration skills with excellent written and verbal ...
... RTL designs - Working with design verification and formal verification teams to verify ... front-end ASIC RTL design Tight-knit collaboration skills with excellent written and verbal ...
ASIC RTL/SoC Design Engineer
San Jose, CA · On-site
$110K - $300K/yr
Lead RTL design, simulation, and verification efforts for TetraMem ASIC/SoC products, ensuring ... Play a mentorship role by guiding and coaching junior engineers, sharing expertise and best ...
ASIC RTL/SoC Design Engineer
San Jose, CA · On-site
$110K - $300K/yr
Lead RTL design, simulation, and verification efforts for TetraMem ASIC/SoC products, ensuring ... Play a mentorship role by guiding and coaching junior engineers, sharing expertise and best ...
... RTL designs - Working with design verification and formal verification teams to verify ... front-end ASIC RTL design Tight-knit collaboration skills with excellent written and verbal ...
... RTL designs - Working with design verification and formal verification teams to verify ... front-end ASIC RTL design Tight-knit collaboration skills with excellent written and verbal ...
Staff RTL Engineer - Ethernet Saratoga, CA Full-Time Join a cutting-edge hardware company building ... MSEE with 8-15 years of ASIC/RTL design experience * Strong expertise in Ethernet 802.3 protocols ...
Staff RTL Engineer - Ethernet Saratoga, CA Full-Time Join a cutting-edge hardware company building ... MSEE with 8-15 years of ASIC/RTL design experience * Strong expertise in Ethernet 802.3 protocols ...
ASIC Design Engineer Responsibilities: * Define and bring up FPGA platforms for pre-silicon ... Map ASIC RTL to FGPA while minimizing code base differences * Create and execute test plans for ...
Quick apply
ASIC Design Engineer Responsibilities: * Define and bring up FPGA platforms for pre-silicon ... Map ASIC RTL to FGPA while minimizing code base differences * Create and execute test plans for ...
Description As an ASIC Design Engineer on the Silicon Security team, you will be responsible for the micro-architecture, RTL design and integration of secure subsystems. Your responsibilities will ...
Description As an ASIC Design Engineer on the Silicon Security team, you will be responsible for the micro-architecture, RTL design and integration of secure subsystems. Your responsibilities will ...
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience. * 4 years of experience in ASIC RTL design, with a focus on ...
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience. * 4 years of experience in ASIC RTL design, with a focus on ...
Asic Rtl Design Engineer information
See San Jose, CA salary details
$110.2K - $121.7K
16% of jobs
$121.7K - $133.2K
3% of jobs
$133.2K - $144.7K
4% of jobs
$148K is the 25th percentile. Wages below this are outliers.
$144.7K - $156.2K
6% of jobs
The median wage is $163.4K / yr.
$156.2K - $167.7K
33% of jobs
$167.7K - $179.2K
3% of jobs
$179.2K - $190.7K
2% of jobs
$198.3K is the 75th percentile. Wages above this are outliers.
$190.7K - $202.2K
12% of jobs
$202.2K - $213.7K
5% of jobs
$213.7K - $225.2K
4% of jobs
$225.2K - $236.7K
12% of jobs
$110.2K
$176K
$236.7K
How much do asic rtl design engineer jobs pay per year?
As of Aug 15, 2026, the average yearly pay for asic rtl design engineer in San Jose, CA is $176,028.00, according to ZipRecruiter salary data. Most workers in this role earn between $154,100.00 and $211,000.00 per year, depending on experience, location, and employer.
What is an ASIC RTL design engineer?
An ASIC RTL Design Engineer is responsible for designing and implementing the digital logic of Application-Specific Integrated Circuits (ASICs) using Hardware Description Languages (HDLs) like Verilog or VHDL. They translate system-level specifications into Register Transfer Level (RTL) code, ensuring functionality, performance, and power efficiency. Their role also involves simulation, synthesis, timing analysis, and debugging to verify and optimize the design. They collaborate with verification, physical design, and firmware teams to ensure seamless integration.
What are the typical daily responsibilities of an ASIC RTL design engineer?
As an ASIC RTL Design Engineer, your daily responsibilities often include designing and verifying Register Transfer Level (RTL) code for specific chip modules, running simulations, and debugging functional issues. You will frequently collaborate with verification engineers, physical design teams, and system architects to ensure the design meets specifications and performance goals. The role also involves attending regular team meetings to coordinate project tasks and document progress. Staying current with evolving industry methodologies and engaging in code reviews are also part of the typical workflow.
What are the key skills and qualifications needed to thrive in the ASIC RTL design engineer position, and why are they important?
To thrive as an ASIC RTL Design Engineer, you need a strong background in digital logic design, Verilog or VHDL coding, and a relevant degree in electrical or computer engineering. Proficiency with industry-standard EDA tools such as Synopsys, Cadence, and ModelSim, as well as familiarity with simulation and synthesis processes, is typically required. Attention to detail, strong problem-solving abilities, and effective communication skills are highly valued in this position. These competencies are essential to ensuring robust, efficient, and collaborative chip development within project timelines.
What are the most commonly searched types of Asic Rtl Design Engineer jobs in San Jose, CA?
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For Asic Rtl Design Engineer jobs in San Jose, CA, the most frequently searched job titles are:
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Job description
- The work will expose the designer to a number of IP including ARM cores, Ethernet, DDR, DMA, PCIE, SATA and *** internal IPs.
- Successful candidates will be responsible for leading, and participating in, the design of leading edge SoC?s in advanced digital CMOS processes.Our RTL Design Engineers are expected contribute in all aspects of SoC design including: Chip definition, Architecture development and modeling, Development of micro-architectural specifications, Conversion of micro-architectural specifications to logic implementation, Verification, emulation, debug, synthesis, and timing closure, Interfacing with physical execution, software, and silicon bring-up teams.
EXPERIENCE AND EDUCATION:
- SoC Architecture; knowledge and hand-on experience from industry ASIC design flow including RTL coding, debugging/verification, and supporting synthesis and timing closure.
- Working knowledge of ARM cores and other I/O standard interfaces. An ideal candidate would also exhibit
- Strong communication and documentation skills, Good organizational, time management and multitasking skills, Strong initiative and discipline to follow-through, Technical leadership. 10+ years of experience.
About Saicon consultants
Sourced by ZipRecruiter
Company size
201 - 500 Employees
Headquarters location
Overland Park, KS, US
Year founded
1998