ASIC RTL Design Engineer
San Jose, CA · On-site
As an ASIC RTL Design Engineer, you will be an integral part of the design and development of cutting-edge System on Chips (SoCs), supporting a dynamic and collaborative environment. The ideal ...
San Jose, CA · On-site
As an ASIC RTL Design Engineer, you will be an integral part of the design and development of cutting-edge System on Chips (SoCs), supporting a dynamic and collaborative environment. The ideal ...
San Jose, CA · On-site
As an ASIC RTL Design Engineer, you will be an integral part of the design and development of cutting-edge System on Chips (SoCs), supporting a dynamic and collaborative environment. The ideal ...
SENIOR ASIC RTL Design Verilog High Speed Memory Interface Experience Logic synthesis & Timing constraints Forward Error Correction (FEC), Bit Rate Error (BER) calculations Integrating Soft IP from ...
SENIOR ASIC RTL Design Verilog High Speed Memory Interface Experience Logic synthesis & Timing constraints Forward Error Correction (FEC), Bit Rate Error (BER) calculations Integrating Soft IP from ...
RTL Engineer - Networking ASIC Saratoga, CA Full-Time Join an innovative hardware company building ... Design packet buffering, queuing, and scheduling microarchitecture * Implement high-speed ...
RTL Engineer - Networking ASIC Saratoga, CA Full-Time Join an innovative hardware company building ... Design packet buffering, queuing, and scheduling microarchitecture * Implement high-speed ...
San Jose, CA · On-site
Our RTL Design Engineers are expected contribute in all aspects of SoC design including: Chip ... SoC Architecture;knowledge and hand-on experience from industry ASIC design flow including RTL ...
San Jose, CA · On-site
Our RTL Design Engineers are expected contribute in all aspects of SoC design including: Chip ... SoC Architecture;knowledge and hand-on experience from industry ASIC design flow including RTL ...
Austin, TX · On-site
S. in Electrical Engineering, Computer Engineering, or Computer Science * 5+ years of experience in ASIC RTL design * Solid foundation in computer architecture and digital logic design * Strong ...
Austin, TX · On-site
S. in Electrical Engineering, Computer Engineering, or Computer Science * 5+ years of experience in ASIC RTL design * Solid foundation in computer architecture and digital logic design * Strong ...
About the role SambaNova Systems is looking for a Principal RTL Design Engineer to own the ... MS or PhD in EE, CE, or CS with 10+ years of experience in ASIC RTL design
About the role SambaNova Systems is looking for a Principal RTL Design Engineer to own the ... MS or PhD in EE, CE, or CS with 10+ years of experience in ASIC RTL design
San Diego, CA · On-site
$127K - $190K/yr
Engineering Group, Engineering Group > DSP Architecture and Design General Summary: A variety of ... This position involves in-depth understanding of the ASIC design flow from RTL to GDS2 and the ...
San Diego, CA · On-site
$127K - $190K/yr
Engineering Group, Engineering Group > DSP Architecture and Design General Summary: A variety of ... This position involves in-depth understanding of the ASIC design flow from RTL to GDS2 and the ...
San Jose, CA · On-site
$82 - $86/hr
Hands-on experience with industry ASIC design flow including RTL coding, debugging/verification ... We deliver agile, scalable talent solutions across IT, engineering, life sciences, clinical, and ...
Quick apply
San Jose, CA · On-site
$82 - $86/hr
Hands-on experience with industry ASIC design flow including RTL coding, debugging/verification ... We deliver agile, scalable talent solutions across IT, engineering, life sciences, clinical, and ...
We're seeking engineers who are energized by working on cutting-edge ASIC design and distributed ... Own ASIC RTL delivery schedules across major milestones by tracking, monitoring, and reporting ...
We're seeking engineers who are energized by working on cutting-edge ASIC design and distributed ... Own ASIC RTL delivery schedules across major milestones by tracking, monitoring, and reporting ...
San Jose, CA · On-site
$60 - $62/hr
Hands-on experience in industry ASIC design flow including RTL coding, debugging/verification, and supporting synthesis and timing closure. * Working knowledge of Client cores and other I/O standard ...
Quick apply
San Jose, CA · On-site
$60 - $62/hr
Hands-on experience in industry ASIC design flow including RTL coding, debugging/verification, and supporting synthesis and timing closure. * Working knowledge of Client cores and other I/O standard ...
San Jose, CA · On-site
$200 - $250/hr
As a Senior ASIC Design Engineer, you will own the complete RTL design lifecycle from micro‑architecture specification through production silicon, working on complex IP design. THE PERSON: The ...
San Jose, CA · On-site
$200 - $250/hr
As a Senior ASIC Design Engineer, you will own the complete RTL design lifecycle from micro‑architecture specification through production silicon, working on complex IP design. THE PERSON: The ...
Richardson, TX · On-site
$125 - $150/hr
This role is ideal for an engineer with strong Verilog/SystemVerilog RTL design experience, a solid understanding of ASIC/SoC development flows, and the ability to collaborate across design ...
Richardson, TX · On-site
$125 - $150/hr
This role is ideal for an engineer with strong Verilog/SystemVerilog RTL design experience, a solid understanding of ASIC/SoC development flows, and the ability to collaborate across design ...
Austin, TX · On-site
$120K - $200K/yr
S. in Electrical Engineering, Computer Engineering, or Computer Science * 5+ years of experience in ASIC RTL design * Solid foundation in computer architecture and digital logic design * Strong ...
Austin, TX · On-site
$120K - $200K/yr
S. in Electrical Engineering, Computer Engineering, or Computer Science * 5+ years of experience in ASIC RTL design * Solid foundation in computer architecture and digital logic design * Strong ...
Austin, TX · On-site
B.S. in Electrical Engineering, Computer Engineering, or Computer Science * 7+ years of industry experience in ASIC RTL design * Mastery of synthesizable SystemVerilog for high-speed, high ...
Austin, TX · On-site
B.S. in Electrical Engineering, Computer Engineering, or Computer Science * 7+ years of industry experience in ASIC RTL design * Mastery of synthesizable SystemVerilog for high-speed, high ...
Richardson, TX · On-site +1
$122K/yr
This role is ideal for an engineer with strong Verilog/SystemVerilog RTL design experience, a solid understanding of ASIC/SoC development flows, and the ability to collaborate across design ...
Richardson, TX · On-site +1
$122K/yr
This role is ideal for an engineer with strong Verilog/SystemVerilog RTL design experience, a solid understanding of ASIC/SoC development flows, and the ability to collaborate across design ...
ASIC/RTL Design Engineer Primary Skills : RTL coding, TCL coding, Python coding, understanding of different CAD tools (synthesis, lint, CDC, RDC, PrimeTime). Location: San Jose CA Duration : 12 ...
ASIC/RTL Design Engineer Primary Skills : RTL coding, TCL coding, Python coding, understanding of different CAD tools (synthesis, lint, CDC, RDC, PrimeTime). Location: San Jose CA Duration : 12 ...
Santa Clara, CA · On-site
$150 - $200/hr
NVIDIA Gruppe in Santa Clara is hiring an ASIC Design Engineer to develop cutting-edge SoC and GPU ... The role involves drafting microarchitecture documents, implementing high-performance RTL, and ...
Santa Clara, CA · On-site
$150 - $200/hr
NVIDIA Gruppe in Santa Clara is hiring an ASIC Design Engineer to develop cutting-edge SoC and GPU ... The role involves drafting microarchitecture documents, implementing high-performance RTL, and ...
Fremont, CA · On-site
Lead RTL design, simulation, and verification efforts for TetraMem ASIC/SoC products, ensuring ... Play a mentorship role by guiding and coaching junior engineers, sharing expertise and best ...
Fremont, CA · On-site
Lead RTL design, simulation, and verification efforts for TetraMem ASIC/SoC products, ensuring ... Play a mentorship role by guiding and coaching junior engineers, sharing expertise and best ...
As a Senior ASIC Design Engineer, you will own the complete RTL design lifecycle from micro-architecture specification through production silicon, working on complex IP design. THE PERSON: The ideal ...
As a Senior ASIC Design Engineer, you will own the complete RTL design lifecycle from micro-architecture specification through production silicon, working on complex IP design. THE PERSON: The ideal ...
Beaverton, OR · On-site
Sr/ ASIC Design Engineer (5+ Years of Experience) DESCRIPTION OF POSITION/DUTIES - * Architect a ... Run LINT and CDC checks on the RTL code and fix accordingly. * Assist with synthesis and FPGA ...
Beaverton, OR · On-site
Sr/ ASIC Design Engineer (5+ Years of Experience) DESCRIPTION OF POSITION/DUTIES - * Architect a ... Run LINT and CDC checks on the RTL code and fix accordingly. * Assist with synthesis and FPGA ...
$23.52 is the 25th percentile. Wages below this are outliers.
$14.90 - $25.57
31% of jobs
The median wage is $32.14 / hr.
$25.57 - $36.23
31% of jobs
$36.23 - $46.90
4% of jobs
$56.23 is the 75th percentile. Wages above this are outliers.
$46.90 - $57.56
10% of jobs
$57.56 - $68.23
9% of jobs
$68.23 - $78.89
5% of jobs
$78.89 - $89.55
0% of jobs
$89.55 - $100.22
8% of jobs
$100.22 - $110.88
0% of jobs
$110.88 - $121.55
0% of jobs
$121.55 - $132.21
1% of jobs
$14
$47
$132
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San Jose, CA • On-site
Other
Medical, Dental, Vision, Life, Retirement
This job post has expired today. Applications are no longer accepted.
Our client is seeking a dedicated ASIC RTL Design Engineer to join their innovative team. As an ASIC RTL Design Engineer, you will be an integral part of the design and development of cutting-edge System on Chips (SoCs), supporting a dynamic and collaborative environment. The ideal candidate will possess strong technical expertise, excellent communication skills, and a proactive approach to problem-solving, which will enable you to thrive and contribute meaningfully within the organization.
Job Title: ASIC RTL Design Engineer
Location: San Jose, CA
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