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Freelance Asic Rtl Design Engineer Jobs in Georgia

Falcomm

ASIC Engineer

Atlanta, GA · On-site

$159K/yr

Falcomm is seeking an ASIC Engineer to support the development of mixed-signal and digital ... Strong experience with RTL design (Verilog/SystemVerilog) and/or analog/mixed-signal IC design

Falcomm

ASIC Engineer

Atlanta, GA · On-site

$159K/yr

Falcomm is seeking an ASIC Engineer to support the development of mixed-signal and digital ... Strong experience with RTL design (Verilog/SystemVerilog) and/or analog/mixed-signal IC design

Falcomm

ASIC Engineer

Atlanta, GA · On-site

$159K/yr

Falcomm is seeking an ASIC Engineer to support the development of mixed-signal and digital ... Strong experience with RTL design (Verilog/SystemVerilog) and/or analog/mixed-signal IC design

Cypress HCM

Senior Design Engineer (PMIC)

Suwanee, GA

$150K - $200K/yr

Senior Design Engineer - Mixed-Signal (PMIC) Location: Suwanee, GA 30024 | Reporting To: Sr. ... Designing/writing microarchitecture and RTL coding using System Verilog * Implementing fine-grain ...

Universal Avionics

FPGA Logic Design Manager

Duluth, GA · On-site

$119K - $153K/yr

Complex Engineering Challenges. * Lead highly technical FPGA and PLD development efforts spanning architecture, RTL design, verification, certification, integration, and system-level problem solving.

Cypress HCM

Senior Analog Design Engineer

Suwanee, GA · On-site

$140K - $180K/yr

Senior Design Engineer - Analog Location: Suwanee, GA 30024 | Reporting To: Sr. Director ... Experience with Verilog RTL coding, including synchronous and asynchronous machines * Experience ...

Avnet, Inc.

Field Application Engineer

Atlanta, GA

... RTL and simulation assistance, system bring up and debug) * Collaborate with field and AMD Xilinx ... Experience with and understanding at systems level, FPGA and ASIC design tools. Experience with ...

Falcomm

IT/EDA Engineer

Atlanta, GA · On-site

Falcomm is seeking an IT/EDA Systems Engineer who will sit at the intersection of IT infrastructure ... Experience supporting RFIC, ASIC, or semiconductor design teams * Experience with HPC clusters or ...

Falcomm

IT/EDA Engineer

Atlanta, GA · On-site

Falcomm is seeking an IT/EDA Systems Engineer who will sit at the intersection of IT infrastructure ... Experience supporting RFIC, ASIC, or semiconductor design teams * Experience with HPC clusters or ...

Falcomm

IT/EDA Engineer

Atlanta, GA · On-site

Falcomm is seeking an IT/EDA Systems Engineer who will sit at the intersection of IT infrastructure ... Experience supporting RFIC, ASIC, or semiconductor design teams * Experience with HPC clusters or ...

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Freelance Asic Rtl Design Engineer information

How much does a Freelance ASIC RTL Design Engineer make?

Freelance ASIC RTL Design Engineers typically earn between $50 and $150 per hour, depending on experience, project complexity, and location. Rates can vary based on expertise in hardware description languages like Verilog or VHDL and familiarity with FPGA or ASIC design tools.

Are freelance ASIC RTL design engineers in demand?

Freelance ASIC RTL design engineers are in demand due to the growing need for custom chip development in industries like telecommunications, AI, and consumer electronics. Skills in hardware description languages such as Verilog or VHDL, along with experience in FPGA prototyping, enhance employability in this competitive field.
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Freelance Asic Rtl Design Engineer jobs near you

ASIC Engineer

Falcomm

Atlanta, GA • On-site

$159K/yr

Full-time

Medical, Dental, Vision, Retirement, PTO

Re-posted 29 days ago

Job description

Are you passionate about building advanced semiconductor systems that power next-generation wireless technologies? At Falcomm, we are transforming innovative semiconductor research into real-world products through energy-efficient RF power amplifier and wireless solutions. Our mission is to push the boundaries of performance, efficiency, and integration in modern communication systems.

Falcomm is seeking an ASIC Engineer to support the development of mixed-signal and digital integrated circuits that interface with our RF technologies. This role will contribute to the design, implementation, and verification of ASIC components within larger system-on-chip platforms. The position requires strong collaboration with RFIC, analog, verification, and system engineering teams to deliver high-performance silicon solutions.

Responsibilities:
  • Design and implement digital and/or mixed-signal ASIC blocks from specification to tapeout
  • Develop RTL (Verilog/SystemVerilog) and/or transistor-level designs depending on focus area
  • Collaborate with RFIC, analog, and system engineers to integrate digital logic within RF and mixed-signal chip architectures.
  • Perform synthesis, timing closure, and power optimization
  • Work with verification engineers to define testbenches and ensure robust design validation
  • Support functional verification and debugging of ASIC components in collaboration with verification teams.
  • Assist with synthesis, timing analysis, and physical implementation activities to ensure design readiness for tape-out.
  • Contribute to silicon bring-up, debugging, and post-silicon validation activities.
  • Document design architecture, implementation details, and verification results.

Requirements

  • Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related discipline.
  • 1-3 years of experience developing and implementing in ASIC design.
  • Strong experience with RTL design (Verilog/SystemVerilog) and/or analog/mixed-signal IC design
  • Solid understanding of digital design fundamentals (timing, clocking, power, etc.)
  • Experience with ASIC tool flows (e.g., Synopsys, Cadence, or similar)
  • Familiarity with verification methodologies (UVM is a plus)
  • Strong problem-solving skills and ability to work across disciplines
  • Must be willing to work full-time, onsite, in Atlanta, GA.
Preferred Skills
  • Strong problem-solving skills in complex digital design areas such as clock domain crossing, timing optimization, and low-power design techniques.
  • Hands-on experience with industry EDA tools including HDL simulators, linting tools, and FPGA development platforms.
  • Proficiency in scripting languages such as Python or TCL to support design automation and verification workflows.

Benefits

  • Competitive Salary and Equity Package
  • Comprehensive Health, Dental, and Vision Insurance
  • 401(k) Retirement Plan
  • Paid Time Off (PTO) and Sick Leave

Disclosure:

  • Falcomm is an Equal Opportunity Employer; employment with Falcomm is governed on the basis of merit, competence and qualifications and will not be influenced in any manner by race, color, religion, gender, national origin/ethnicity, veteran status, disability status, age, sexual orientation, gender identity, marital status, mental or physical disability or any other legally protected status.
  • Applicants wishing to view a copy of Falcomm's Affirmative Action Plan for veterans and individuals with disabilities, or applicants requiring reasonable accommodation to the application/interview process should notify Falcomm.
  • To conform to U.S. Government export regulations, including the International Traffic in Arms Regulations (ITAR) you must be a U.S. citizen, lawful permanent resident of the U.S., protected individual as defined by 8 U.S.C. 1324b(a)(3), or eligible to obtain the required authorizations from the U.S. Department of State.

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