ASIC Engineer
Atlanta, GA · On-site
$159K/yr
Falcomm is seeking an ASIC Engineer to support the development of mixed-signal and digital ... Strong experience with RTL design (Verilog/SystemVerilog) and/or analog/mixed-signal IC design
Quick apply
ASIC Engineer
Atlanta, GA · On-site
$159K/yr
Falcomm is seeking an ASIC Engineer to support the development of mixed-signal and digital ... Strong experience with RTL design (Verilog/SystemVerilog) and/or analog/mixed-signal IC design
ASIC Engineer
Atlanta, GA · On-site
$159K/yr
Falcomm is seeking an ASIC Engineer to support the development of mixed-signal and digital ... Strong experience with RTL design (Verilog/SystemVerilog) and/or analog/mixed-signal IC design
ASIC Engineer
Atlanta, GA · On-site
$159K/yr
Falcomm is seeking an ASIC Engineer to support the development of mixed-signal and digital ... Strong experience with RTL design (Verilog/SystemVerilog) and/or analog/mixed-signal IC design
ASIC Engineer
$159K/yr
Falcomm is seeking an ASIC Engineer to support the development of mixed-signal and digital ... Strong experience with RTL design (Verilog/SystemVerilog) and/or analog/mixed-signal IC design
ASIC Engineer
$159K/yr
Falcomm is seeking an ASIC Engineer to support the development of mixed-signal and digital ... Strong experience with RTL design (Verilog/SystemVerilog) and/or analog/mixed-signal IC design
Principal Digital Design Engineer
Duluth, GA · On-site
$125K/yr
Mentor and train junior engineers and New College Grad engineers Qualifications * Education ... Fluent in Verilog RTL coding and ASIC design methodology * Expertise in digital design ...
Principal Digital Design Engineer
Duluth, GA · On-site
$125K/yr
Mentor and train junior engineers and New College Grad engineers Qualifications * Education ... Fluent in Verilog RTL coding and ASIC design methodology * Expertise in digital design ...
Mentor and train junior engineers and New College Grad engineers Qualifications * Education ... Fluent in Verilog RTL coding and ASIC design methodology * Expertise in digital design ...
Quick apply
Mentor and train junior engineers and New College Grad engineers Qualifications * Education ... Fluent in Verilog RTL coding and ASIC design methodology * Expertise in digital design ...
Principal Digital Design Engineer
Duluth, GA · On-site
$125K/yr
Mentor and train junior engineers and New College Grad engineers Qualifications * Education ... Fluent in Verilog RTL coding and ASIC design methodology * Expertise in digital design ...
Principal Digital Design Engineer
Duluth, GA · On-site
$125K/yr
Mentor and train junior engineers and New College Grad engineers Qualifications * Education ... Fluent in Verilog RTL coding and ASIC design methodology * Expertise in digital design ...
Mentor and train junior engineers and New College Grad engineers Qualifications * Education ... Fluent in Verilog RTL coding and ASIC design methodology * Expertise in digital design ...
Mentor and train junior engineers and New College Grad engineers Qualifications * Education ... Fluent in Verilog RTL coding and ASIC design methodology * Expertise in digital design ...
Senior Design Engineer (PMIC)
$150K - $200K/yr
Senior Design Engineer - Mixed-Signal (PMIC) Location: Suwanee, GA 30024 | Reporting To: Sr. ... Designing/writing microarchitecture and RTL coding using System Verilog * Implementing fine-grain ...
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Senior Design Engineer (PMIC)
$150K - $200K/yr
Senior Design Engineer - Mixed-Signal (PMIC) Location: Suwanee, GA 30024 | Reporting To: Sr. ... Designing/writing microarchitecture and RTL coding using System Verilog * Implementing fine-grain ...
FPGA Logic Design Manager
$119K - $153K/yr
Complex Engineering Challenges. * Lead highly technical FPGA and PLD development efforts spanning architecture, RTL design, verification, certification, integration, and system-level problem solving.
FPGA Logic Design Manager
$119K - $153K/yr
Complex Engineering Challenges. * Lead highly technical FPGA and PLD development efforts spanning architecture, RTL design, verification, certification, integration, and system-level problem solving.
FPGA Logic Design Manager
Duluth, GA · On-site
$119K - $153K/yr
Complex Engineering Challenges. * Lead highly technical FPGA and PLD development efforts spanning architecture, RTL design, verification, certification, integration, and system-level problem solving.
FPGA Logic Design Manager
Duluth, GA · On-site
$119K - $153K/yr
Complex Engineering Challenges. * Lead highly technical FPGA and PLD development efforts spanning architecture, RTL design, verification, certification, integration, and system-level problem solving.
Senior Analog Design Engineer
$140K - $180K/yr
Senior Design Engineer - Analog Location: Suwanee, GA 30024 | Reporting To: Sr. Director ... Experience with Verilog RTL coding, including synchronous and asynchronous machines * Experience ...
Quick apply
Senior Analog Design Engineer
$140K - $180K/yr
Senior Design Engineer - Analog Location: Suwanee, GA 30024 | Reporting To: Sr. Director ... Experience with Verilog RTL coding, including synchronous and asynchronous machines * Experience ...
Field Application Engineer
Atlanta, GA · On-site
... RTL and simulation assistance, system bring up and debug) * Collaborate with field and AMD Xilinx ... Experience with and understanding at systems level, FPGA and ASIC design tools. Experience with ...
Field Application Engineer
Atlanta, GA · On-site
... RTL and simulation assistance, system bring up and debug) * Collaborate with field and AMD Xilinx ... Experience with and understanding at systems level, FPGA and ASIC design tools. Experience with ...
... RTL and simulation assistance, system bring up and debug) * Collaborate with field and AMD Xilinx ... Experience with and understanding at systems level, FPGA and ASIC design tools. Experience with ...
... RTL and simulation assistance, system bring up and debug) * Collaborate with field and AMD Xilinx ... Experience with and understanding at systems level, FPGA and ASIC design tools. Experience with ...
Falcomm is seeking an IT/EDA Systems Engineer who will sit at the intersection of IT infrastructure ... Experience supporting RFIC, ASIC, or semiconductor design teams * Experience with HPC clusters or ...
Falcomm is seeking an IT/EDA Systems Engineer who will sit at the intersection of IT infrastructure ... Experience supporting RFIC, ASIC, or semiconductor design teams * Experience with HPC clusters or ...
IT/EDA Engineer
Atlanta, GA · On-site
Falcomm is seeking an IT/EDA Systems Engineer who will sit at the intersection of IT infrastructure ... Experience supporting RFIC, ASIC, or semiconductor design teams * Experience with HPC clusters or ...
Quick apply
IT/EDA Engineer
Atlanta, GA · On-site
Falcomm is seeking an IT/EDA Systems Engineer who will sit at the intersection of IT infrastructure ... Experience supporting RFIC, ASIC, or semiconductor design teams * Experience with HPC clusters or ...
IT/EDA Engineer
Atlanta, GA · On-site
Falcomm is seeking an IT/EDA Systems Engineer who will sit at the intersection of IT infrastructure ... Experience supporting RFIC, ASIC, or semiconductor design teams * Experience with HPC clusters or ...
IT/EDA Engineer
Atlanta, GA · On-site
Falcomm is seeking an IT/EDA Systems Engineer who will sit at the intersection of IT infrastructure ... Experience supporting RFIC, ASIC, or semiconductor design teams * Experience with HPC clusters or ...
Drupal Developer
Atlanta, GA · On-site +1
Georgia Tech Professional Education is looking to utilize freelance developers to assist our in-house team in the design, development, testing, and implementation of customized Drupal websites. This ...
Drupal Developer
Atlanta, GA · On-site +1
Georgia Tech Professional Education is looking to utilize freelance developers to assist our in-house team in the design, development, testing, and implementation of customized Drupal websites. This ...
The RTL is the connective tissue between Corporate Technology and the Region - translating ... Empower regional GIS staff, Innovation Ambassadors, Model Based Design Coaches, and AI Champions to ...
The RTL is the connective tissue between Corporate Technology and the Region - translating ... Empower regional GIS staff, Innovation Ambassadors, Model Based Design Coaches, and AI Champions to ...
The RTL is the connective tissue between Corporate Technology and the Region - translating ... Empower regional GIS staff, Innovation Ambassadors, Model Based Design Coaches, and AI Champions to ...
The RTL is the connective tissue between Corporate Technology and the Region - translating ... Empower regional GIS staff, Innovation Ambassadors, Model Based Design Coaches, and AI Champions to ...
NOT A FREELANCE POSITION - THIS IS FOR FULL-TIME EMPLOYMENT ONLY***** Join Our Team at Clever Fox ... Implement design and functionality updates based on client feedback. * Ensure websites follow ...
Quick apply
NOT A FREELANCE POSITION - THIS IS FOR FULL-TIME EMPLOYMENT ONLY***** Join Our Team at Clever Fox ... Implement design and functionality updates based on client feedback. * Ensure websites follow ...
Freelance Asic Rtl Design Engineer information
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$159K/yr
Full-time
Medical, Dental, Vision, Retirement, PTO
Posted 13 days ago
Job description
Are you passionate about building advanced semiconductor systems that power next-generation wireless technologies? At Falcomm, we are transforming innovative semiconductor research into real-world products through energy-efficient RF power amplifier and wireless solutions. Our mission is to push the boundaries of performance, efficiency, and integration in modern communication systems.
Falcomm is seeking an ASIC Engineer to support the development of mixed-signal and digital integrated circuits that interface with our RF technologies. This role will contribute to the design, implementation, and verification of ASIC components within larger system-on-chip platforms. The position requires strong collaboration with RFIC, analog, verification, and system engineering teams to deliver high-performance silicon solutions.
Responsibilities:- Design and implement digital and/or mixed-signal ASIC blocks from specification to tapeout
- Develop RTL (Verilog/SystemVerilog) and/or transistor-level designs depending on focus area
- Collaborate with RFIC, analog, and system engineers to integrate digital logic within RF and mixed-signal chip architectures.
- Perform synthesis, timing closure, and power optimization
- Work with verification engineers to define testbenches and ensure robust design validation
- Support functional verification and debugging of ASIC components in collaboration with verification teams.
- Assist with synthesis, timing analysis, and physical implementation activities to ensure design readiness for tape-out.
- Contribute to silicon bring-up, debugging, and post-silicon validation activities.
- Document design architecture, implementation details, and verification results.
Requirements
- Bachelor’s or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related discipline.
- 1-3 years of experience developing and implementing in ASIC design.
- Strong experience with RTL design (Verilog/SystemVerilog) and/or analog/mixed-signal IC design
- Solid understanding of digital design fundamentals (timing, clocking, power, etc.)
- Experience with ASIC tool flows (e.g., Synopsys, Cadence, or similar)
- Familiarity with verification methodologies (UVM is a plus)
- Strong problem-solving skills and ability to work across disciplines
- Must be willing to work full-time, onsite, in Atlanta, GA.
- Strong problem-solving skills in complex digital design areas such as clock domain crossing, timing optimization, and low-power design techniques.
- Hands-on experience with industry EDA tools including HDL simulators, linting tools, and FPGA development platforms.
- Proficiency in scripting languages such as Python or TCL to support design automation and verification workflows.
Benefits
- Competitive Salary and Equity Package
- Comprehensive Health, Dental, and Vision Insurance
- 401(k) Retirement Plan
- Paid Time Off (PTO) and Sick Leave
Disclosure:
- Falcomm is an Equal Opportunity Employer; employment with Falcomm is governed on the basis of merit, competence and qualifications and will not be influenced in any manner by race, color, religion, gender, national origin/ethnicity, veteran status, disability status, age, sexual orientation, gender identity, marital status, mental or physical disability or any other legally protected status.
- Applicants wishing to view a copy of Falcomm’s Affirmative Action Plan for veterans and individuals with disabilities, or applicants requiring reasonable accommodation to the application/interview process should notify Falcomm.
- To conform to U.S. Government export regulations, including the International Traffic in Arms Regulations (ITAR) you must be a U.S. citizen, lawful permanent resident of the U.S., protected individual as defined by 8 U.S.C. 1324b(a)(3), or eligible to obtain the required authorizations from the U.S. Department of State.