Toolchain / Digital Design Engineer
Lincolnton, GA ยท On-site
$115K/yr
... design ... Responsibilities - Develop and extend EDA/RTL compilation tools and scripts (Python, C++, and/or ...
Quick apply
Lincolnton, GA ยท On-site
$115K/yr
... design ... Responsibilities - Develop and extend EDA/RTL compilation tools and scripts (Python, C++, and/or ...
Quick apply
Lincolnton, GA ยท On-site
$115K/yr
... design ... Responsibilities - Develop and extend EDA/RTL compilation tools and scripts (Python, C++, and/or ...
Atlanta, GA ยท On-site
$130K/yr
... design ... Responsibilities - Develop and extend EDA/RTL compilation tools and scripts (Python, C++, and/or ...
Quick apply
Atlanta, GA ยท On-site
$130K/yr
... design ... Responsibilities - Develop and extend EDA/RTL compilation tools and scripts (Python, C++, and/or ...
Lincolnton, GA ยท On-site
$115K/yr
... design ... Responsibilities - Develop and extend EDA/RTL compilation tools and scripts (Python, C++, and/or ...
Quick apply
Lincolnton, GA ยท On-site
$115K/yr
... design ... Responsibilities - Develop and extend EDA/RTL compilation tools and scripts (Python, C++, and/or ...
Lincolnton, GA ยท On-site
$115K/yr
... design ... Responsibilities - Develop and extend EDA/RTL compilation tools and scripts (Python, C++, and/or ...
Quick apply
Lincolnton, GA ยท On-site
$115K/yr
... design ... Responsibilities - Develop and extend EDA/RTL compilation tools and scripts (Python, C++, and/or ...
The ideal candidate will have hands-on experience with the full RTL-to-GDSII flow and a desire to ... Design and implement logic and state machines using SystemVerilog/Verilog RTL. Develop, debug, and ...
Quick apply
The ideal candidate will have hands-on experience with the full RTL-to-GDSII flow and a desire to ... Design and implement logic and state machines using SystemVerilog/Verilog RTL. Develop, debug, and ...
The ideal candidate will have hands-on experience with the full RTL-to-GDSII flow and a desire to ... Design and implement logic and state machines using SystemVerilog/Verilog RTL. Develop, debug, and ...
Quick apply
The ideal candidate will have hands-on experience with the full RTL-to-GDSII flow and a desire to ... Design and implement logic and state machines using SystemVerilog/Verilog RTL. Develop, debug, and ...
$119K - $153K/yr
Managing technical execution across requirements, RTL design, low-level verification, hardware integration, and problem resolution * Driving compliance with DO-254 processes, airworthiness ...
$119K - $153K/yr
Managing technical execution across requirements, RTL design, low-level verification, hardware integration, and problem resolution * Driving compliance with DO-254 processes, airworthiness ...
Duluth, GA ยท On-site
$119K - $153K/yr
Managing technical execution across requirements, RTL design, low-level verification, hardware integration, and problem resolution * Driving compliance with DO-254 processes, airworthiness ...
Duluth, GA ยท On-site
$119K - $153K/yr
Managing technical execution across requirements, RTL design, low-level verification, hardware integration, and problem resolution * Driving compliance with DO-254 processes, airworthiness ...
$150K - $200K/yr
Senior Design Engineer - Mixed-Signal (PMIC) Location: Suwanee, GA 30024 | Reporting To: Sr. ... Designing/writing microarchitecture and RTL coding using System Verilog * Implementing fine-grain ...
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$150K - $200K/yr
Senior Design Engineer - Mixed-Signal (PMIC) Location: Suwanee, GA 30024 | Reporting To: Sr. ... Designing/writing microarchitecture and RTL coding using System Verilog * Implementing fine-grain ...
$159K/yr
Design and implement digital and/or mixed-signal ASIC blocks from specification to tapeout * Develop RTL (Verilog/SystemVerilog) and/or transistor-level designs depending on focus area * Collaborate ...
$159K/yr
Design and implement digital and/or mixed-signal ASIC blocks from specification to tapeout * Develop RTL (Verilog/SystemVerilog) and/or transistor-level designs depending on focus area * Collaborate ...
Propose, architect, and design RTL in Verilog for use in a mixed-signal integrated circuit * Contribute as part of a highly experienced team of engineers with extensive cross-functional skill set
Propose, architect, and design RTL in Verilog for use in a mixed-signal integrated circuit * Contribute as part of a highly experienced team of engineers with extensive cross-functional skill set
Atlanta, GA ยท On-site
$159K/yr
Design and implement digital and/or mixed-signal ASIC blocks from specification to tapeout * Develop RTL (Verilog/SystemVerilog) and/or transistor-level designs depending on focus area * Collaborate ...
Quick apply
Atlanta, GA ยท On-site
$159K/yr
Design and implement digital and/or mixed-signal ASIC blocks from specification to tapeout * Develop RTL (Verilog/SystemVerilog) and/or transistor-level designs depending on focus area * Collaborate ...
Atlanta, GA ยท On-site
$159K/yr
Design and implement digital and/or mixed-signal ASIC blocks from specification to tapeout * Develop RTL (Verilog/SystemVerilog) and/or transistor-level designs depending on focus area * Collaborate ...
Atlanta, GA ยท On-site
$159K/yr
Design and implement digital and/or mixed-signal ASIC blocks from specification to tapeout * Develop RTL (Verilog/SystemVerilog) and/or transistor-level designs depending on focus area * Collaborate ...
Duluth, GA ยท On-site
$125K/yr
Propose, architect, and design RTL in Verilog for use in a mixed-signal integrated circuit * Contribute as part of a highly experienced team of engineers with extensive cross-functional skill set
Duluth, GA ยท On-site
$125K/yr
Propose, architect, and design RTL in Verilog for use in a mixed-signal integrated circuit * Contribute as part of a highly experienced team of engineers with extensive cross-functional skill set
Duluth, GA ยท On-site
$125K/yr
Propose, architect, and design RTL in Verilog for use in a mixed-signal integrated circuit * Contribute as part of a highly experienced team of engineers with extensive cross-functional skill set
Quick apply
Duluth, GA ยท On-site
$125K/yr
Propose, architect, and design RTL in Verilog for use in a mixed-signal integrated circuit * Contribute as part of a highly experienced team of engineers with extensive cross-functional skill set
$140K - $180K/yr
Senior Design Engineer - Analog Location: Suwanee, GA 30024 | Reporting To: Sr. Director ... Experience with Verilog RTL coding, including synchronous and asynchronous machines * Experience ...
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$140K - $180K/yr
Senior Design Engineer - Analog Location: Suwanee, GA 30024 | Reporting To: Sr. Director ... Experience with Verilog RTL coding, including synchronous and asynchronous machines * Experience ...
The RTL is the connective tissue between Corporate Technology and the Region - translating ... Empower regional GIS staff, Innovation Ambassadors, Model Based Design Coaches, and AI Champions to ...
The RTL is the connective tissue between Corporate Technology and the Region - translating ... Empower regional GIS staff, Innovation Ambassadors, Model Based Design Coaches, and AI Champions to ...
The RTL is the connective tissue between Corporate Technology and the Region - translating ... Empower regional GIS staff, Innovation Ambassadors, Model Based Design Coaches, and AI Champions to ...
The RTL is the connective tissue between Corporate Technology and the Region - translating ... Empower regional GIS staff, Innovation Ambassadors, Model Based Design Coaches, and AI Champions to ...
The RTL is the connective tissue between Corporate Technology and the Region - translating ... Empower regional GIS staff, Innovation Ambassadors, Model Based Design Coaches, and AI Champions to ...
The RTL is the connective tissue between Corporate Technology and the Region - translating ... Empower regional GIS staff, Innovation Ambassadors, Model Based Design Coaches, and AI Champions to ...
The RTL is the connective tissue between Corporate Technology and the Region -- translating ... Empower regional GIS staff, Innovation Ambassadors, Model Based Design Coaches, and AI Champions to ...
The RTL is the connective tissue between Corporate Technology and the Region -- translating ... Empower regional GIS staff, Innovation Ambassadors, Model Based Design Coaches, and AI Champions to ...
$68K - $75.8K
0% of jobs
$75.8K - $83.6K
0% of jobs
$83.6K - $91.5K
1% of jobs
$91.5K - $99.3K
0% of jobs
$99.3K - $107.1K
0% of jobs
$110.4K is the 25th percentile. Wages below this are outliers.
$107.1K - $115K
57% of jobs
$118.3K is the 75th percentile. Wages above this are outliers.
$115K - $122.8K
38% of jobs
$122.8K - $130.6K
0% of jobs
$130.6K - $138.4K
1% of jobs
$138.4K - $146.3K
1% of jobs
$146.3K - $154.1K
1% of jobs
$68K
$117.7K
$154.1K
To thrive as an RTL Design engineer, you need a solid background in digital logic design, computer architecture, and proficiency in hardware description languages such as Verilog or VHDL, typically supported by a degree in electrical or computer engineering. Familiarity with EDA tools like Synopsys, Cadence, or Mentor Graphics, and experience with FPGA/ASIC flows, are highly valuable, as are relevant industry certifications. Strong problem-solving skills, attention to detail, and effective communication foster successful collaboration with verification and physical design teams. These skills are crucial for delivering robust, efficient hardware solutions in complex chip development projects.
A typical day for an RTL Design engineer involves writing and optimizing RTL code, running simulations, debugging designs, and reviewing results from verification teams. Collaboration is key, as you will frequently interact with verification engineers, physical design teams, and architects to ensure the design meets both functional and performance requirements. You may also participate in design reviews, resolve issues found during testing, and work with project managers to meet deadlines. This cross-functional teamwork creates a dynamic environment where communication and problem-solving skills are highly valued, helping ensure the successful delivery of silicon products.
An RTL (Register Transfer Level) Design job involves designing and implementing digital circuits using hardware description languages (HDLs) like Verilog or VHDL. RTL engineers translate high-level specifications into synthesizable logic, ensuring functionality, power efficiency, and performance. They collaborate with verification engineers to test and debug designs before fabrication. This role is crucial in developing ASICs, FPGAs, and other digital hardware components.

$115K/yr
Part-time
Re-posted 4 days ago