Lincolnton, GA · On-site
$115K/yr
Responsibilities - Develop and extend EDA/RTL compilation tools and scripts (Python, C++, and/or ... Engineering, or Computer Science. - Demonstrated expertise in EDA toolchains, RTL design (Verilog ...
Quick apply
Lincolnton, GA · On-site
$115K/yr
Responsibilities - Develop and extend EDA/RTL compilation tools and scripts (Python, C++, and/or ... Engineering, or Computer Science. - Demonstrated expertise in EDA toolchains, RTL design (Verilog ...
Lincolnton, GA · On-site
$115K/yr
Responsibilities - Develop and extend EDA/RTL compilation tools and scripts (Python, C++, and/or ... Engineering, or Computer Science. - Demonstrated expertise in EDA toolchains, RTL design (Verilog ...
Quick apply
Lincolnton, GA · On-site
$115K/yr
Responsibilities - Develop and extend EDA/RTL compilation tools and scripts (Python, C++, and/or ... Engineering, or Computer Science. - Demonstrated expertise in EDA toolchains, RTL design (Verilog ...
Atlanta, GA · On-site
$130K/yr
Responsibilities - Develop and extend EDA/RTL compilation tools and scripts (Python, C++, and/or ... Engineering, or Computer Science. - Demonstrated expertise in EDA toolchains, RTL design (Verilog ...
Quick apply
Atlanta, GA · On-site
$130K/yr
Responsibilities - Develop and extend EDA/RTL compilation tools and scripts (Python, C++, and/or ... Engineering, or Computer Science. - Demonstrated expertise in EDA toolchains, RTL design (Verilog ...
Lincolnton, GA · On-site
$115K/yr
Responsibilities - Develop and extend EDA/RTL compilation tools and scripts (Python, C++, and/or ... Engineering, or Computer Science. - Demonstrated expertise in EDA toolchains, RTL design (Verilog ...
Quick apply
Lincolnton, GA · On-site
$115K/yr
Responsibilities - Develop and extend EDA/RTL compilation tools and scripts (Python, C++, and/or ... Engineering, or Computer Science. - Demonstrated expertise in EDA toolchains, RTL design (Verilog ...
Suwanee, GA · On-site
$150K - $200K/yr
Senior Design Engineer - Mixed-Signal (PMIC) Location: Suwanee, GA 30024 | Reporting To: Sr. ... Designing/writing microarchitecture and RTL coding using System Verilog * Implementing fine-grain ...
Quick apply
Suwanee, GA · On-site
$150K - $200K/yr
Senior Design Engineer - Mixed-Signal (PMIC) Location: Suwanee, GA 30024 | Reporting To: Sr. ... Designing/writing microarchitecture and RTL coding using System Verilog * Implementing fine-grain ...
Propose, architect, and design RTL in Verilog for use in a mixed-signal integrated circuit * Contribute as part of a highly experienced team of engineers with extensive cross-functional skill set
Propose, architect, and design RTL in Verilog for use in a mixed-signal integrated circuit * Contribute as part of a highly experienced team of engineers with extensive cross-functional skill set
Propose, architect, and design RTL in Verilog for use in a mixed-signal integrated circuit * Contribute as part of a highly experienced team of engineers with extensive cross-functional skill set
Quick apply
Propose, architect, and design RTL in Verilog for use in a mixed-signal integrated circuit * Contribute as part of a highly experienced team of engineers with extensive cross-functional skill set
Duluth, GA · On-site
$125K/yr
Propose, architect, and design RTL in Verilog for use in a mixed-signal integrated circuit * Contribute as part of a highly experienced team of engineers with extensive cross-functional skill set
Duluth, GA · On-site
$125K/yr
Propose, architect, and design RTL in Verilog for use in a mixed-signal integrated circuit * Contribute as part of a highly experienced team of engineers with extensive cross-functional skill set
$119K - $153K/yr
Complex Engineering Challenges. * Lead highly technical FPGA and PLD development efforts spanning architecture, RTL design, verification, certification, integration, and system-level problem solving.
$119K - $153K/yr
Complex Engineering Challenges. * Lead highly technical FPGA and PLD development efforts spanning architecture, RTL design, verification, certification, integration, and system-level problem solving.
Duluth, GA · On-site
$119K - $153K/yr
Complex Engineering Challenges. * Lead highly technical FPGA and PLD development efforts spanning architecture, RTL design, verification, certification, integration, and system-level problem solving.
Duluth, GA · On-site
$119K - $153K/yr
Complex Engineering Challenges. * Lead highly technical FPGA and PLD development efforts spanning architecture, RTL design, verification, certification, integration, and system-level problem solving.
Suwanee, GA · On-site
$140K - $180K/yr
Senior Design Engineer - Analog Location: Suwanee, GA 30024 | Reporting To: Sr. Director ... Experience with Verilog RTL coding, including synchronous and asynchronous machines * Experience ...
Quick apply
Suwanee, GA · On-site
$140K - $180K/yr
Senior Design Engineer - Analog Location: Suwanee, GA 30024 | Reporting To: Sr. Director ... Experience with Verilog RTL coding, including synchronous and asynchronous machines * Experience ...
$159K/yr
Falcomm is seeking an ASIC Engineer to support the development of mixed-signal and digital ... Strong experience with RTL design (Verilog/SystemVerilog) and/or analog/mixed-signal IC design
$159K/yr
Falcomm is seeking an ASIC Engineer to support the development of mixed-signal and digital ... Strong experience with RTL design (Verilog/SystemVerilog) and/or analog/mixed-signal IC design
Atlanta, GA · On-site
$159K/yr
Falcomm is seeking an ASIC Engineer to support the development of mixed-signal and digital ... Strong experience with RTL design (Verilog/SystemVerilog) and/or analog/mixed-signal IC design
Atlanta, GA · On-site
$159K/yr
Falcomm is seeking an ASIC Engineer to support the development of mixed-signal and digital ... Strong experience with RTL design (Verilog/SystemVerilog) and/or analog/mixed-signal IC design
Atlanta, GA · On-site
$159K/yr
Falcomm is seeking an ASIC Engineer to support the development of mixed-signal and digital ... Strong experience with RTL design (Verilog/SystemVerilog) and/or analog/mixed-signal IC design
Quick apply
Atlanta, GA · On-site
$159K/yr
Falcomm is seeking an ASIC Engineer to support the development of mixed-signal and digital ... Strong experience with RTL design (Verilog/SystemVerilog) and/or analog/mixed-signal IC design
$150K - $165K/yr
Description The Hardware Design Engineer will participate in development projects in a rapidly ... Some senior level positions require use of RTL coding using Verilog or VHDL and other FPGA tools.
Quick apply
$150K - $165K/yr
Description The Hardware Design Engineer will participate in development projects in a rapidly ... Some senior level positions require use of RTL coding using Verilog or VHDL and other FPGA tools.
... Design Closure, RTL and simulation assistance, system bring up and debug) * Collaborate with field and AMD Xilinx factory resources to develop and deliver technical proposals to customer project ...
... Design Closure, RTL and simulation assistance, system bring up and debug) * Collaborate with field and AMD Xilinx factory resources to develop and deliver technical proposals to customer project ...
... Design Closure, RTL and simulation assistance, system bring up and debug) * Collaborate with field and AMD Xilinx factory resources to develop and deliver technical proposals to customer project ...
... Design Closure, RTL and simulation assistance, system bring up and debug) * Collaborate with field and AMD Xilinx factory resources to develop and deliver technical proposals to customer project ...
The RTL is the connective tissue between Corporate Technology and the Region - translating ... Empower regional GIS staff, Innovation Ambassadors, Model Based Design Coaches, and AI Champions to ...
The RTL is the connective tissue between Corporate Technology and the Region - translating ... Empower regional GIS staff, Innovation Ambassadors, Model Based Design Coaches, and AI Champions to ...
The RTL is the connective tissue between Corporate Technology and the Region - translating ... Empower regional GIS staff, Innovation Ambassadors, Model Based Design Coaches, and AI Champions to ...
The RTL is the connective tissue between Corporate Technology and the Region - translating ... Empower regional GIS staff, Innovation Ambassadors, Model Based Design Coaches, and AI Champions to ...
The RTL is the connective tissue between Corporate Technology and the Region - translating ... Empower regional GIS staff, Innovation Ambassadors, Model Based Design Coaches, and AI Champions to ...
The RTL is the connective tissue between Corporate Technology and the Region - translating ... Empower regional GIS staff, Innovation Ambassadors, Model Based Design Coaches, and AI Champions to ...
$34.2K - $43.3K
2% of jobs
$43.3K - $52.3K
11% of jobs
$57.2K is the 25th percentile. Wages below this are outliers.
$52.3K - $61.4K
23% of jobs
The median wage is $67.2K / yr.
$61.4K - $70.4K
22% of jobs
$70.4K - $79.5K
17% of jobs
$79.7K is the 75th percentile. Wages above this are outliers.
$79.5K - $88.5K
9% of jobs
$88.5K - $97.6K
6% of jobs
$97.6K - $106.7K
3% of jobs
$106.7K - $115.7K
3% of jobs
$115.7K - $124.8K
2% of jobs
$124.8K - $133.8K
1% of jobs
$34.2K
$74.4K
$133.8K
As an RTL Design Engineer, you can advance into roles such as Senior Design Engineer, Technical Lead, or even Design Manager as you gain experience and demonstrate strong technical expertise. Many professionals also transition into related areas such as verification engineering, system architecture, or product management. The role offers continuous learning opportunities and exposure to cutting-edge semiconductor technology, making it ideal for those interested in expanding their skillset. Career progression is often supported by successful project delivery, ongoing education, and active collaboration within multidisciplinary teams.
To thrive as an RTL Design Engineer, you need a strong background in digital logic design, proficiency in hardware description languages like Verilog or VHDL, and a bachelor's or master’s degree in electrical or computer engineering. Experience with industry-standard EDA tools such as Synopsys or Cadence, and knowledge of FPGA or ASIC design flow, are typically required. Strong problem-solving, teamwork, and communication skills are essential for effective collaboration with verification teams and other engineering groups. These competencies are critical to accurately translate system requirements into robust, manufacturable hardware designs within fast-paced project timelines.
An RTL (Register Transfer Level) Design Engineer is responsible for designing and implementing digital circuits using hardware description languages like VHDL or Verilog. They develop and optimize high-performance, power-efficient designs for ASICs or FPGAs based on system requirements. Their role includes writing RTL code, performing simulations, debugging issues, and collaborating with verification, physical design, and architecture teams. RTL engineers ensure the design meets functional, timing, and power constraints before handing it off for further implementation.
$115K/yr
Part-time
Posted 29 days ago
