ZipRecruiter

Log In

2

Full Time Asic Rtl Design Engineer Jobs (NOW HIRING)

SambaNova

Senior RTL Design Engineer

Austin, TX · On-site

S. in Electrical Engineering, Computer Engineering, or Computer Science * 5+ years of experience in ASIC RTL design * Solid foundation in computer architecture and digital logic design * Strong ...

Qualcomm

Processor ASIC RTL Design Engineer

San Diego, CA · On-site

$127K - $190K/yr

Engineering Group, Engineering Group > DSP Architecture and Design General Summary: A variety of ... This position involves in-depth understanding of the ASIC design flow from RTL to GDS2 and the ...

SambaNova

Senior RTL Design Engineer

Austin, TX · On-site

$120K - $200K/yr

Exposure to a full ASIC development cycle through tape-out and production silicon * Interest in or ... Benefits Summary for US-Based, Full-Time Employment Positions SambaNova offers a competitive total ...

SambaNova

Principal RTL Design Engineer

Austin, TX · On-site

B.S. in Electrical Engineering, Computer Engineering, or Computer Science * 7+ years of industry experience in ASIC RTL design * Mastery of synthesizable SystemVerilog for high-speed, high ...

IC Enable

RTL Design Engineer

Richardson, TX · On-site +1

$122K/yr

This role is ideal for an engineer with strong Verilog/SystemVerilog RTL design experience, a solid understanding of ASIC/SoC development flows, and the ability to collaborate across design ...

TetraMem INC

ASIC RTL/SoC Design Engineer

Fremont, CA · On-site

Lead RTL design, simulation, and verification efforts for TetraMem ASIC/SoC products, ensuring ... Play a mentorship role by guiding and coaching junior engineers, sharing expertise and best ...

ServerLogic

Senior ASIC Design Engineer

Beaverton, OR · On-site

Sr/ ASIC Design Engineer (5+ Years of Experience) DESCRIPTION OF POSITION/DUTIES - * Architect a ... Run LINT and CDC checks on the RTL code and fix accordingly. * Assist with synthesis and FPGA ...

TetraMem INC

ASIC RTL/SoC Design Engineer

Fremont, CA · On-site

Lead RTL design, simulation, and verification efforts for TetraMem ASIC/SoC products, ensuring ... Play a mentorship role by guiding and coaching junior engineers, sharing expertise and best ...

SambaNova

Principal RTL Design Engineer

Austin, TX · On-site

$180K - $255K/yr

... ASIC RTL design * Mastery of synthesizable SystemVerilog for high-speed, high-performance ASICs ... Benefits Summary for US-Based, Full-Time Employment Positions SambaNova offers a competitive total ...

SambaNova

Principal RTL Design Engineer

San Jose, CA · On-site

MS or PhD in EE, CE, or CS with 10+ years of experience in ASIC RTL design Base Salary Range: Base ... Benefits Summary for US-Based, Full-Time Employment Positions SambaNova offers a competitive total ...

TetraMem, Inc.

ASIC RTL/SoC Design Engineer

San Jose, CA · On-site

$110K - $300K/yr

Lead RTL design, simulation, and verification efforts for TetraMem ASIC/SoC products, ensuring ... Play a mentorship role by guiding and coaching junior engineers, sharing expertise and best ...

Apple

ASIC Design and Integration Engineer

Beaverton, OR · On-site

Apple's Silicon Engineering team is looking for a highly skilled and motivated ASIC Design Engineer ... Develop RTL using SystemVerilog and perform synthesis. Verification: Engage with simulation-based ...

next page

Showing results 1-20

All JobsFull Time JobsTechnology JobsDesktop Support JobsDesktop Engineer JobsFull Time Asic Rtl Design Engineer Jobs

Full Time Asic Rtl Design Engineer information

See salary details

$94K

$150.2K

$202K

How much do full time asic rtl design engineer jobs pay per year?

As of Sep 10, 2026, the average yearly pay for full time asic rtl design engineer in the United States is $150,195.00, according to ZipRecruiter salary data. Most workers in this role earn between $131,500.00 and $180,000.00 per year, depending on experience, location, and employer.

What is a full time ASIC RTL design engineer?

Full Time ASIC RTL Design Engineers are professionals who specialize in designing digital circuits at the Register Transfer Level (RTL) for Application Specific Integrated Circuits (ASICs). They use hardware description languages like Verilog or VHDL to create, simulate, and verify complex digital systems that are manufactured as custom chips. Their work typically involves collaborating with other engineers to optimize performance, area, and power consumption, as well as ensuring that the design meets specified requirements. These engineers play a crucial role in the development of chips used in various applications, including consumer electronics, automotive systems, and telecommunications.

What are some common challenges full time ASIC RTL design engineers face when collaborating with verification teams?

A common challenge for ASIC RTL Design Engineers is ensuring that the design specifications are interpreted consistently between design and verification teams. Misalignment can lead to time-consuming bug fixes and delays in the project schedule. Effective communication, regular design reviews, and close collaboration are vital to catching issues early and maintaining project momentum. Additionally, engineers must often adapt quickly to evolving requirements or last-minute changes, which requires flexibility and strong problem-solving skills.

What are the key skills and qualifications needed to thrive as a full time ASIC RTL design engineer, and why are they important?

To thrive as a Full Time ASIC RTL Design Engineer, you need a solid background in digital logic design, computer architecture, and proficiency in Hardware Description Languages (HDLs) like Verilog or VHDL, typically supported by a degree in electrical or computer engineering. Familiarity with EDA tools such as Synopsys, Cadence, or Mentor Graphics, and knowledge of simulation, synthesis, and timing analysis, are crucial, with some roles requiring verification or DFT experience. Strong analytical thinking, attention to detail, and effective communication skills set exceptional engineers apart in team environments. These skills and qualities are essential for creating reliable, efficient hardware designs and ensuring successful silicon implementations in a competitive technology landscape.
More about Full Time Asic Rtl Design Engineer jobs

What cities are hiring for Full Time Asic Rtl Design Engineer jobs?

Cities with the most Full Time Asic Rtl Design Engineer job openings:

What are the most commonly searched types of Asic Rtl Design Engineer jobs?

The most popular types of Asic Rtl Design Engineer jobs are:

What states have the most Full Time Asic Rtl Design Engineer jobs?

States with the most job openings for Full Time Asic Rtl Design Engineer jobs include:

What are popular job titles related to Full Time Asic Rtl Design Engineer jobs?

For Full Time Asic Rtl Design Engineer jobs, the most frequently searched job titles are:

Full Time Asic Rtl Design Engineer jobs near you
Infographic showing various Full Time Asic Rtl Design Engineer job openings in the United States as of September 2026, with employment types broken down into 1% Internship, 89% Full Time, 7% Part Time, and 3% Contract. Highlights an 81% Physical, 4% Hybrid, and 15% Remote job distribution, with an average salary of $150,195 per year, or $72.2 per hour.

Senior RTL Design Engineer

Austin, TX • On-site

SambaNova
See more jobs at SambaNovaexternal

Full-time

Posted 20 days ago

Job description

About the team About the role

The RTL design team builds the compute datapath, on-chip network, and memory subsystems inside SambaNova's RDU AI accelerator. Their work spans microarchitecture through tape-out: RTL implementation, PPA trade-offs, quality gates like lint, CDC, and LEC, and timing closure with 

About the role

SambaNova RTL Design Engineers design component units of the Reconfigurable Dataflow Unit (RDU) ASICs behind our AI acceleration systems. You'll own blocks within a larger subsystem, contributing sections of the microarchitecture specification, writing and debugging the RTL, and carrying your blocks through implementation, tape-out, and silicon bring-up. You'll work alongside principal engineers, architects, design verification, and physical design, and take on larger blocks as you build depth in our architecture

Required Qualifications
  • B.S. in Electrical Engineering, Computer Engineering, or Computer Science
  • 5+ years of experience in ASIC RTL design
  • Solid foundation in computer architecture and digital logic design
  • Strong SystemVerilog RTL design skills for high-speed, high-performance ASICs
  • Experience making design decisions that trade off power, performance, and area
  • Knowledge of industry-standard interconnects and protocols including AXI, PCIe, Ethernet, and HBM or DDR
  • Experience with digital logic synthesis tools and static timing analysis
  • Proficiency with industry-standard tools for linting, clock domain crossing, and logical equivalence checking
  • Experience implementing SystemVerilog Assertions to check design intent
  • Familiarity with tools and simulators for hardware performance analysis and tuning
  • Familiarity with Git for managing release cycles
  • Scripting skills in Python and Linux shell
Preferred Qualifications
  • M.S. or Ph.D. in Electrical Engineering, Computer Engineering, or Computer Science
  • Exposure to a full ASIC development cycle through tape-out and production silicon
  • Interest in or knowledge of AI workload acceleration techniques
  • Experience with low-power design techniques such as clock gating and DVFS at advanced process nodes
  • Exposure to emulation or FPGA prototyping platforms for pre-silicon validation

Apply