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Full Time Asic Rtl Design Engineer Jobs (NOW HIRING)

PRINCIPAL RTL DESIGN

Boise, ID · On-site

$129K - $133K/yr

Overview Micron Technology seeks a Principal RTL Design Engineer to lead the development of ... Strong experience with ASIC low‐power design methodologies, including UPF‐based power intent ...

RTL Design Engineer As an RTL Engineer at Etched, you will be critical in ensuring that our AI ... both our existing and upcoming ASIC designs. In this role, you will work closely with ...

Apple's Silicon Engineering team is looking for a highly skilled and motivated ASIC Design Engineer ... Develop RTL using SystemVerilog and perform synthesis. Verification: Engage with simulation-based ...

Be an integral part of the System ASIC Design team to help develop and improve our RTL and SOC designs * Collaborate with architects, ASIC designers, and verification engineers to design ...

Apple's Silicon Engineering team is looking for a highly skilled and motivated ASIC Design Engineer ... Develop RTL using SystemVerilog and perform synthesis. Verification: Engage with simulation-based ...

Apple's Silicon Engineering team is looking for a highly skilled and motivated ASIC Design Engineer ... Develop RTL using SystemVerilog and perform synthesis. Verification: Engage with simulation-based ...

Apple's Silicon Engineering team is looking for a highly skilled and motivated ASIC Design Engineer ... Develop RTL using SystemVerilog and perform synthesis. Verification: Engage with simulation-based ...

RTL Design Engineer

San Jose, CA · On-site

$150K - $275K/yr

Job Summary As an RTL Engineer at Etched, you will be critical in ensuring that our AI chips ... both our existing and upcoming ASIC designs. In this role, you will work closely with ...

RTL Design Engineer

San Jose, CA · On-site

$150K - $275K/yr

Job Summary As an RTL Engineer at Etched, you will be critical in ensuring that our AI chips ... both our existing and upcoming ASIC designs. In this role, you will work closely with ...

The engineer will collaborate with architecture, verification, and physical design teams to deliver ... Strong knowledge of ASIC front-end design flows including RTL design, functional verification ...

The engineer will collaborate with architecture, verification, and physical design teams to deliver ... Strong knowledge of ASIC front-end design flows including RTL design, functional verification ...

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Full Time Asic Rtl Design Engineer information

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$94K

$150.2K

$202K

How much do full time asic rtl design engineer jobs pay per year?

As of Aug 21, 2026, the average yearly pay for full time asic rtl design engineer in the United States is $150,195.00, according to ZipRecruiter salary data. Most workers in this role earn between $131,500.00 and $180,000.00 per year, depending on experience, location, and employer.

What is a full time ASIC RTL design engineer?

Full Time ASIC RTL Design Engineers are professionals who specialize in designing digital circuits at the Register Transfer Level (RTL) for Application Specific Integrated Circuits (ASICs). They use hardware description languages like Verilog or VHDL to create, simulate, and verify complex digital systems that are manufactured as custom chips. Their work typically involves collaborating with other engineers to optimize performance, area, and power consumption, as well as ensuring that the design meets specified requirements. These engineers play a crucial role in the development of chips used in various applications, including consumer electronics, automotive systems, and telecommunications.

What are some common challenges full time ASIC RTL design engineers face when collaborating with verification teams?

A common challenge for ASIC RTL Design Engineers is ensuring that the design specifications are interpreted consistently between design and verification teams. Misalignment can lead to time-consuming bug fixes and delays in the project schedule. Effective communication, regular design reviews, and close collaboration are vital to catching issues early and maintaining project momentum. Additionally, engineers must often adapt quickly to evolving requirements or last-minute changes, which requires flexibility and strong problem-solving skills.

What are the key skills and qualifications needed to thrive as a full time ASIC RTL design engineer, and why are they important?

To thrive as a Full Time ASIC RTL Design Engineer, you need a solid background in digital logic design, computer architecture, and proficiency in Hardware Description Languages (HDLs) like Verilog or VHDL, typically supported by a degree in electrical or computer engineering. Familiarity with EDA tools such as Synopsys, Cadence, or Mentor Graphics, and knowledge of simulation, synthesis, and timing analysis, are crucial, with some roles requiring verification or DFT experience. Strong analytical thinking, attention to detail, and effective communication skills set exceptional engineers apart in team environments. These skills and qualities are essential for creating reliable, efficient hardware designs and ensuring successful silicon implementations in a competitive technology landscape.
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Infographic showing various Full Time Asic Rtl Design Engineer job openings in the United States as of August 2026, with employment types broken down into 89% Full Time, 7% Part Time, and 4% Contract. Highlights an 83% Physical, 5% Hybrid, and 12% Remote job distribution, with an average salary of $150,195 per year, or $72.2 per hour.

$129K - $133K/yr

Full-time

Medical, Dental, Vision, PTO

This job post has expired today. Applications are no longer accepted.


Job description

Overview Micron Technology seeks a Principal RTL Design Engineer to lead the development of high‐quality DRAM digital and mixed‐signal IP in Boise, Idaho. The role covers the full RTL design lifecycle—architecture, implementation, signoff—while meeting aggressive power, performance, and area (PPA) targets. Responsibilities Own and drive RTL design for DRAM digital and mixed‐signal IP from specification through silicon‐ready signoff. Architect and deliver high‐performance, power‐ and area‐efficient RTL designs aligned with product requirements. Perform and sign off front‐end quality checks, including lint, CDC/RDC, synthesis, UPF, and timing QoR. Collaborate closely with physical design, verification, and architecture teams to achieve timing closure and PPA goals. Improve design quality and efficiency by refining methodologies, driving automation, and enhancing RTL design flows. Minimum Qualifications Master's degree in Electrical Engineering with 8+ years of experience, or Bachelor's degree with 10+ years of pre‐silicon RTL design experience. Proven ownership of complex RTL/IP development from micro‐architecture definition through handoff to physical design. Strong experience with ASIC low‐power design methodologies, including UPF‐based power intent and power‐aware CDC/RDC. In‐depth knowledge of RTL design, logic synthesis, functional verification, and static timing analysis (STA). Proficiency in Verilog/SystemVerilog and industry‐standard simulation and front‐end tools. Preferred Qualifications Extensive background in DRAM or other memory compose architectures and development. Deep knowledge of CDC, RDC, STA, and low‐power techniques in advanced ASIC technology nodes. Experience designing complex digital logic and/or mixed‐signal‐interfacing circuits. Familiarity with CMOS digital and analog‐integrated circuit concepts and their system‐level impact. Excellent interpersonal skills with the ability to influence multi‐functional teams and technical leadership. Benefits Micron offers a comprehensive benefits program that includes medical, dental, and vision plans, income protection, paid family leave, paid time‐off, and paid holidays. For additional details, refer to the Benefits Guide available on micron.com/careers/benefits. EEO Statement Micron is a proud equal opportunity workplace and an affirmative action employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, age, national origin, citizenship status, disability, protected veteran status, gender identity or any other factor protected by applicable federal, state, or local laws. #J-18808-Ljbffr