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Full Time Asic Rtl Design Engineer Jobs (NOW HIRING)

Apple

ASIC Design Engineer - Pixel IP DMA

Cupertino, CA

$126.80K - $190.90K/yr

... RTL designs - Working with design verification and formal verification teams to verify ... front-end ASIC RTL design Tight-knit collaboration skills with excellent written and verbal ...

Mythic

RTL Design Engineer

Palo Alto, CA

$120K - $225K/yr

We're hiring experienced RTL Design Engineers from junior to senior levels to play a key role in designing and implementing the components that will bring our next-generation AI processors to life.

Mythic

RTL Design Engineer

Austin, TX

$120K - $225K/yr

We're hiring experienced RTL Design Engineers from junior to senior levels to play a key role in designing and implementing the components that will bring our next-generation AI processors to life.

Apple

ASIC Design Engineer - Pixel IP DMA

Cupertino, CA · On-site

$147.40K - $272.10K/yr

... RTL designs - Working with design verification and formal verification teams to verify ... front-end ASIC RTL design Tight-knit collaboration skills with excellent written and verbal ...

Etched

RTL Design Engineer

San Jose, CA · On-site

$150K - $275K/yr

Job Summary As an RTL Engineer at Etched, you will be critical in ensuring that our AI chips ... both our existing and upcoming ASIC designs. In this role, you will work closely with ...

Mythic

RTL Design Engineer

Palo Alto, CA · On-site

$120K - $225K/yr

We're hiring experienced RTL Design Engineers from junior to senior levels to play a key role in designing and implementing the components that will bring our next-generation AI processors to life.

Etched

RTL Design Engineer

San Jose, CA · On-site

$150K - $275K/yr

Job Summary As an RTL Engineer at Etched, you will be critical in ensuring that our AI chips ... both our existing and upcoming ASIC designs. In this role, you will work closely with ...

Apple

ASIC Design Engineer - Pixel IP DMA

Cupertino, CA · On-site

$147.40K - $272.10K/yr

... RTL designs - Working with design verification and formal verification teams to verify ... front-end ASIC RTL design Tight-knit collaboration skills with excellent written and verbal ...

Mythic

RTL Design Engineer

Austin, TX

$120K - $225K/yr

We're hiring experienced RTL Design Engineers from junior to senior levels to play a key role in designing and implementing the components that will bring our next-generation AI processors to life.

Mythic

RTL Design Engineer

Austin, TX

$120K - $225K/yr

We're hiring experienced RTL Design Engineers from junior to senior levels to play a key role in designing and implementing the components that will bring our next-generation AI processors to life.

Teradyne

RTL Design Engineer

Reading, MA · On-site

$123.10K - $196.90K/yr

Opportunity Overview Teradyne's Silicon Technology Engineering (STE), Digital ASIC Group is ... Developing specifications, micro-architecture, and RTL design of mission critical blocks in ...

Mythic

RTL Design Engineer

Palo Alto, CA

$120K - $225K/yr

We're hiring experienced RTL Design Engineers from junior to senior levels to play a key role in designing and implementing the components that will bring our next-generation AI processors to life.

Apple

ASIC Design Engineer - Pixel IP DMA

Cupertino, CA

$126.80K - $190.90K/yr

... RTL designs - Working with design verification and formal verification teams to verify ... front-end ASIC RTL design Tight-knit collaboration skills with excellent written and verbal ...

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All JobsFull Time Asic Rtl Design Engineer Jobs

Full Time Asic Rtl Design Engineer information

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$94K

$150.2K

$202K

How much do full time asic rtl design engineer jobs pay per year?

As of May 30, 2026, the average yearly pay for full time asic rtl design engineer in the United States is $150,195.00, according to ZipRecruiter salary data. Most workers in this role earn between $131,500.00 and $180,000.00 per year, depending on experience, location, and employer.

What are the key skills and qualifications needed to thrive as a Full Time ASIC RTL Design Engineer, and why are they important?

To thrive as a Full Time ASIC RTL Design Engineer, you need a solid background in digital logic design, computer architecture, and proficiency in Hardware Description Languages (HDLs) like Verilog or VHDL, typically supported by a degree in electrical or computer engineering. Familiarity with EDA tools such as Synopsys, Cadence, or Mentor Graphics, and knowledge of simulation, synthesis, and timing analysis, are crucial, with some roles requiring verification or DFT experience. Strong analytical thinking, attention to detail, and effective communication skills set exceptional engineers apart in team environments. These skills and qualities are essential for creating reliable, efficient hardware designs and ensuring successful silicon implementations in a competitive technology landscape.

What are some common challenges Full Time ASIC RTL Design Engineers face when collaborating with verification teams?

A common challenge for ASIC RTL Design Engineers is ensuring that the design specifications are interpreted consistently between design and verification teams. Misalignment can lead to time-consuming bug fixes and delays in the project schedule. Effective communication, regular design reviews, and close collaboration are vital to catching issues early and maintaining project momentum. Additionally, engineers must often adapt quickly to evolving requirements or last-minute changes, which requires flexibility and strong problem-solving skills.

What are Full Time ASIC RTL Design Engineers?

Full Time ASIC RTL Design Engineers are professionals who specialize in designing digital circuits at the Register Transfer Level (RTL) for Application Specific Integrated Circuits (ASICs). They use hardware description languages like Verilog or VHDL to create, simulate, and verify complex digital systems that are manufactured as custom chips. Their work typically involves collaborating with other engineers to optimize performance, area, and power consumption, as well as ensuring that the design meets specified requirements. These engineers play a crucial role in the development of chips used in various applications, including consumer electronics, automotive systems, and telecommunications.
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Full Time Asic Rtl Design Engineer jobs near you
Infographic showing various Full Time Asic Rtl Design Engineer job openings in the United States as of May 2026, with employment types broken down into 1% As Needed, 94% Full Time, and 5% Contract. Highlights an 71% Physical, 4% Hybrid, and 25% Remote job distribution, with an average salary of $150,195 per year, or $72.2 per hour.
Senior ASIC (Front-End) Design Engineer

Senior ASIC (Front-End) Design Engineer

Ethernovia, Inc.

San Jose, CA • On-site

Full-time

Medical, Dental, Vision

Posted 9 days ago

Job description

About Ethernovia, Inc.
Ethernovia is developing the future of Ethernet-based networks to realize the full potential of software-defined and autonomous vehicles, robotics and other intelligent machines. Founded in 2018, the company's breakthrough data transport and acceleration technology is ushering in a new era of connectivity and capabilities in the vehicle and at the edge, including highly reliable autonomy, over-the-air servicing and AI-backed applications.
Ethernovia's co-founders are serial technology entrepreneurs with multiple prior successful ventures together. We are well-funded and backed by some of the worlds' leading technology investors, having secured $154M ($90+M Series-B and $64M Series-A) in total funding to date:
  • Ethernovia Raises Over $90 Million Series B to Scale Leading-Edge Autonomy and Physical AI Networking Chips
  • Ethernovia Raises $64 Million to Accelerate the Revolution of Vehicle Networks | Business Wire
    • (financial backers include: Porsche SE, Qualcomm, AMD, Western Digital, Maverick Silicon, Socratic Partners, Conduit Capital, and CDIB-TEN Capital)

Ethernovia has been recognized in EE Times' prestigious list of the Top 100 Startups for 2025.
  • March 2026: Ethernovia Announces HSB-Enabled Networking Board for NVIDIA Holoscan Platforms
  • January 2024: Our CEO Ramin Shirani Named MotorTrend Software-Defined Vehicle Innovator Awards Winner (ethernovia.com)
  • September 2023: Continental and Ethernovia Announce Partnership to Develop Automotive Switch in 7nm - Ethernovia
  • Connected Car News: Helios, Continental, Ethernovia, Avanci, BMW, Mapbox, Porsche, SEMA, Honda, UltraSense, Flex Logix, Diodes Inc., Garmin, Toyota & Caruso | auto connected car news

With talented employees on 4 continents, we have filed 50+ patents to date.
Join Ethernovia's team to make a lasting impact on the future of packet processor-centric networking solutions to support the real-time sensor, Physical AI, and control data demands of software-defined autonomy across vehicles, robots and intelligent machines. Come share in our success with pre-IPO shares, competitive compensation, and great benefits while growing your knowledge and career with world class talent. We are looking for talented engineers and leaders who have an entrepreneurial spirit and want to drive cutting edge designs from concept to silicon to the future of mobility.
Senior ASIC Front-End Design Engineer
Summary:
  • As a Senior ASIC Front-End Design Engineer, you will be responsible for all aspects of digital SoC design, from micro-architecture specification, RTL, verification, synthesis, lint, CDC, LEC, and static timing analysis to deliver a design meeting target power, performance, and area goals.
  • Work with system architects, software, hardware, and verification engineers to plan, architect, design, implement, and deliver advanced automotive communication semiconductors and systems.
  • You will be on the leading edge of the development and definition of advanced, high-performance custom silicon that embodies functions from a wide range of protocols, algorithms, and applications.
  • Expected to flesh out product definitions with precise specifications of: an ASIC's internal and external interactions, data flow, processing algorithms across a number of disciplines, resource management, and software interfaces.
  • You will be a trusted self-starter who can work with very little guidance or oversight.
  • This position is located in: San Jose, CA (Hybrid)

Key Qualifications:
  • BS and/or MS in Electrical Engineering, Computer Science, or related field
  • Minimum 10+ years of ASIC RTL design and/or architecture experience
  • Proven track record with the development of complex SoCs
  • Strong understanding of digital design fundamentals and methodologies
  • In-depth knowledge of Verilog/System Verilog and simulation tools.
  • Self-motivated and able to work effectively both independently and in a team

Additional Success Factors:
Experience in any of the following areas:
  • Networking (Ethernet MAC, PHY, Switching, TCP/IP, security, PCIe and other industry standard protocols)
  • Video standards, protocols, processing
  • Digital signal processing filters
  • IP integration (SerDes, controllers, processors, etc.)
  • Perl, TCL, C/C++, Make

Personal Skills:
  • Excellent communication/documentation skills.
  • Attention to details.
  • Collaboration across multidisciplinary and international teams.

What You Can Expect from Ethernovia:
  • Technology depth and breadth expansion that can't be found in a large company
  • Opportunity to grow your career as the company grows
  • Pre IPO stock options
  • Cutting edge technology
  • World class team
  • Competitive base salary
  • Flexible hours
  • Medical, dental and vision insurance for employees

Salary Range:
  • The actual offered base salary for U.S. locations will vary depending on factors such as work location, individual qualifications, specializations, experience, skills, job-related knowledge, and internal equity. The annual salary range for this position is $200,000 - $300,000. The compensation package will also include incentive compensation in the form of pre-IPO ISO options, in addition to base salary and a full range of medical and other benefits.

#LI-Hybrid

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