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Asic Physical Design Jobs (NOW HIRING)

K2 Space

OR

$170K - $250K/yr

The Role We are seeking a Senior ASIC Physical Design Engineer to help implement advanced SoCs that power next-generation satellite and space systems. In this role, you will contribute to the full ...

K2 Space

OR

$190K - $280K/yr

The Role We are looking for a Principal ASIC Physical Design Engineer to lead the implementation of complex SoCs for next-generation satellite and space systems. You will own the full physical design ...

Jane Street

ASIC Physical Design Engineer

New York, NY · On-site

$148K - $153K/yr

About the Position We are looking to hire an ASIC Physical Design Engineer to help us design, test, and deploy advanced hardware. As part of our Ultra Low Latency team, you'll have the opportunity to ...

Jane Street

ASIC Physical Design Engineer

New York, NY

$148K - $153K/yr

About the Position We are looking to hire an ASIC Physical Design Engineer to help us design, test, and deploy advanced hardware. As part of our Ultra Low Latency team, you'll have the opportunity to ...

K2 Space

Senior ASIC Physical Design Engineer

Seattle, WA · On-site

$170K - $250K/yr

The Role We are seeking a Senior ASIC Physical Design Engineer to help implement advanced SoCs that power next-generation satellite and space systems. In this role, you will contribute to the full ...

K2 Space

Senior ASIC Physical Design Engineer

$170K - $250K/yr

The Role We are seeking a Senior ASIC Physical Design Engineer to help implement advanced SoCs that power next-generation satellite and space systems. In this role, you will contribute to the full ...

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Asic Physical Design information

See salary details

$95K

$141.5K

How much do asic physical design jobs pay per year?

As of Aug 1, 2026, the average yearly pay for asic physical design in the United States is $139,408.00, according to ZipRecruiter salary data. Most workers in this role earn between $136,000.00 and $140,000.00 per year, depending on experience, location, and employer.

What is the difference between Asic Physical Design vs Asic Verification Engineer?

AspectAsic Physical DesignAsic Verification Engineer
Primary FocusImplementing physical layout, placement, routing of ASICsVerifying functionality and performance of ASIC designs
Skills & CertificationsVLSI design, EDA tools, CMOS fabrication knowledgeHardware description languages, simulation tools, testbench development
Work EnvironmentDesign teams, CAD tools, EDA softwareSimulation labs, testing environments, design verification teams
Industry UsageFoundries, semiconductor companies, chip design firmsASIC design companies, semiconductor firms, EDA tool providers

While both roles are integral to ASIC development, Asic Physical Design focuses on the physical implementation of chip layouts, whereas Asic Verification Engineer concentrates on testing and validating the design to ensure it meets specifications.

What are ASIC Physical Design engineers?

ASIC Physical Design engineers are professionals who take a digital circuit design and transform it into a physical layout that can be manufactured as an integrated circuit (IC) chip. They are responsible for tasks like floorplanning, placement, clock tree synthesis, routing, and ensuring the chip meets timing, power, and area requirements. Their work is critical in bridging the gap between a chip's logical design and its actual fabrication in silicon. ASIC Physical Design engineers use Electronic Design Automation (EDA) tools to optimize and verify the chip design before manufacturing. They play a key role in delivering high-performance, reliable, and cost-effective semiconductors.

What are the key skills and qualifications needed to thrive as an ASIC Physical Design Engineer, and why are they important?

To thrive as an ASIC Physical Design Engineer, you need a solid background in electrical engineering, digital logic design, and experience with the ASIC design flow, often supported by a relevant degree. Proficiency with EDA tools such as Cadence, Synopsys, or Mentor Graphics, and familiarity with scripting languages like TCL or Perl, are typically required. Strong problem-solving skills, attention to detail, and effective communication enhance collaboration within cross-functional teams. These capabilities ensure the efficient design, optimization, and delivery of high-performance, manufacturable integrated circuits.

What are some common challenges faced by ASIC Physical Design engineers during the tape-out phase, and how can they be addressed?

ASIC Physical Design engineers often encounter challenges such as meeting tight timing closure requirements, resolving signal integrity issues, and managing power consumption during the tape-out phase. These challenges require close collaboration with verification, synthesis, and DFT teams, as well as the use of industry-standard EDA tools for thorough analysis and optimization. Proactive communication, rigorous design reviews, and adopting a structured sign-off checklist can help address potential bottlenecks and ensure a successful tape-out.
More about Asic Physical Design jobs
What cities are hiring for Asic Physical Design jobs? Cities with the most Asic Physical Design job openings:
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Asic Physical Design jobs near you
Infographic showing various Asic Physical Design job openings in the United States as of July 2026, with employment types broken down into 26% As Needed, 71% Full Time, 2% Contract, and 1% Summer. Highlights an 85% Physical, 9% Hybrid, and 6% Remote job distribution, with an average salary of $139,408 per year, or $67 per hour.

ASIC Physical Design Engineer, Principal

ForwardEdge ASIC LLC

Saint Paul, MN

$200K - $220K/yr

Other

Medical, Retirement, PTO

Posted 4 days ago

Job description

Position Description: At ForwardEdge ASIC we specialize in best-in-class ASIC technology, 100% domestically traceable microelectronic solutions designed for performance in commercial, aerospace, defense, and security sectors. FEASIC operates a full-scale ASIC design shop with cross-disciplinary fluency between digital logic, analog/mixed-signal design, and physical layout, and sits at the intersection of advanced ASIC, FPGA, and microelectronics design. As a wholly owned subsidiary of Lockheed Martin, we combine the agility of a startup with the stability and scale of a Fortune 100 leader. We operate in a nimble, fast-paced environment of 80+ highly experienced and specialized engineers with over 25 years of ASIC/FPGA experience and more than 300 patents. Position SummaryWe are looking for highly experienced ASIC Physical Design / Static Time Analysis (PD/STA) Engineer to work onsite in our St. Paul, MN office to support ASICs, IPs and Chiplet designs. This role is targeted at senior level candidates who can operate with a high degree of RTL2GDS PD implementation and sign-off for tape out.Key Responsibilities • Lead and collaborate with Analog, Verification, Logic and Physical design team members on all design implementation aspects from Synthesis to Tape-Out of various IPs, test chips and SoC/ASIC designs. • Lead with hands-on experience with synthesis, block and chip level implementation with industry standard PnR, STA and EMIR flows and tools• Lead end-to-end timing closure at block/chip levels including MCMM flows and ECO flows • Collaborate with cross functional teams to problem solve solutions across new and changing tools, flows and methodologies• Mentor junior and senior PD engineers through technical reviews, methodology guidance, and hands-on support.• Improve productivity through automation, infrastructure, and methodology enhancements.• Support project planning by identifying risks, tracking progress, and communicating status to technical and program leadership.Qualifications • BS in Electrical, Electronics, Computer Engineering, or 15 years of experience in related field or MS in Electrical, Electronics, Computer Engineering, or 12 years of experience in related field or Ph.D. with 8 years of experience in related field• Experience in advanced technology nodes and understanding of deep sub-micron design problems/solutions and ability to drive design closure in a fast-paced environment• Strong experience in SOC/ASIC design flows, tools and methodologies.• Knowledge of low power design flows such as power gating, multi-Vt, Voltage scaling techniques• Excellent understanding of logic design fundamentals and gate/transistor level implementation• Strong programming skills in Tcl/Perl/Shell/Python• Effective communicator with the ability to influence cross-functional teams.What We Offer• Work-Life Balance: Flexible 9/80 work schedule with every other Friday off• Competitive Comp & Benefits: Healthcare and medical coverage options, 401(k) retirement benefits with company contribution, generous holidays and PTO• Incentives: Eligibility for short-term and long-term incentive programsJoin ForwardEdge ASIC and be part of a team that thrives on innovation and excellence in ASIC design. Together, we build the technology that enables a safer, more resilient world. $200,000.00 - $220,000.00 Annually

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