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Asic Physical Design Jobs (NOW HIRING)

K2 Space

OR

$170K - $250K/yr

The Role We are seeking a Senior ASIC Physical Design Engineer to help implement advanced SoCs that power next-generation satellite and space systems. In this role, you will contribute to the full ...

K2 Space

OR · On-site

$190K - $280K/yr

The Role We are looking for a Principal ASIC Physical Design Engineer to lead the implementation of complex SoCs for next-generation satellite and space systems. You will own the full physical design ...

Jane Street

ASIC Physical Design Engineer

New York, NY · On-site

$148K - $153K/yr

About the Position We are looking to hire an ASIC Physical Design Engineer to help us design, test, and deploy advanced hardware. As part of our Ultra Low Latency team, you'll have the opportunity to ...

K2 Space

Senior ASIC Physical Design Engineer

Seattle, WA · On-site

$170K - $250K/yr

The Role We are seeking a Senior ASIC Physical Design Engineer to help implement advanced SoCs that power next-generation satellite and space systems. In this role, you will contribute to the full ...

K2 Space

Senior ASIC Physical Design Engineer

Seattle, WA · On-site

$170K - $250K/yr

The Role We are seeking a Senior ASIC Physical Design Engineer to help implement advanced SoCs that power next-generation satellite and space systems. In this role, you will contribute to the full ...

Jane Street

ASIC Physical Design Engineer

New York, NY

$148K - $153K/yr

About the Position We are looking to hire an ASIC Physical Design Engineer to help us design, test, and deploy advanced hardware. As part of our Ultra Low Latency team, you'll have the opportunity to ...

K2 Space

Senior ASIC Physical Design Engineer

$170K - $250K/yr

The Role We are seeking a Senior ASIC Physical Design Engineer to help implement advanced SoCs that power next-generation satellite and space systems. In this role, you will contribute to the full ...

K2 Space

Principal ASIC Physical Design Engineer

$190K - $280K/yr

The Role We are looking for a Principal ASIC Physical Design Engineer to lead the implementation of complex SoCs for next-generation satellite and space systems. You will own the full physical design ...

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Asic Physical Design information

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$95K

$141.5K

How much do asic physical design jobs pay per year?

As of Jul 11, 2026, the average yearly pay for asic physical design in the United States is $139,408.00, according to ZipRecruiter salary data. Most workers in this role earn between $136,000.00 and $140,000.00 per year, depending on experience, location, and employer.

What is the difference between Asic Physical Design vs Asic Verification Engineer?

AspectAsic Physical DesignAsic Verification Engineer
Primary FocusImplementing physical layout, placement, routing of ASICsVerifying functionality and performance of ASIC designs
Skills & CertificationsVLSI design, EDA tools, CMOS fabrication knowledgeHardware description languages, simulation tools, testbench development
Work EnvironmentDesign teams, CAD tools, EDA softwareSimulation labs, testing environments, design verification teams
Industry UsageFoundries, semiconductor companies, chip design firmsASIC design companies, semiconductor firms, EDA tool providers

While both roles are integral to ASIC development, Asic Physical Design focuses on the physical implementation of chip layouts, whereas Asic Verification Engineer concentrates on testing and validating the design to ensure it meets specifications.

What are ASIC Physical Design engineers?

ASIC Physical Design engineers are professionals who take a digital circuit design and transform it into a physical layout that can be manufactured as an integrated circuit (IC) chip. They are responsible for tasks like floorplanning, placement, clock tree synthesis, routing, and ensuring the chip meets timing, power, and area requirements. Their work is critical in bridging the gap between a chip's logical design and its actual fabrication in silicon. ASIC Physical Design engineers use Electronic Design Automation (EDA) tools to optimize and verify the chip design before manufacturing. They play a key role in delivering high-performance, reliable, and cost-effective semiconductors.

What are the key skills and qualifications needed to thrive as an ASIC Physical Design Engineer, and why are they important?

To thrive as an ASIC Physical Design Engineer, you need a solid background in electrical engineering, digital logic design, and experience with the ASIC design flow, often supported by a relevant degree. Proficiency with EDA tools such as Cadence, Synopsys, or Mentor Graphics, and familiarity with scripting languages like TCL or Perl, are typically required. Strong problem-solving skills, attention to detail, and effective communication enhance collaboration within cross-functional teams. These capabilities ensure the efficient design, optimization, and delivery of high-performance, manufacturable integrated circuits.

What are some common challenges faced by ASIC Physical Design engineers during the tape-out phase, and how can they be addressed?

ASIC Physical Design engineers often encounter challenges such as meeting tight timing closure requirements, resolving signal integrity issues, and managing power consumption during the tape-out phase. These challenges require close collaboration with verification, synthesis, and DFT teams, as well as the use of industry-standard EDA tools for thorough analysis and optimization. Proactive communication, rigorous design reviews, and adopting a structured sign-off checklist can help address potential bottlenecks and ensure a successful tape-out.
More about Asic Physical Design jobs
What cities are hiring for Asic Physical Design jobs? Cities with the most Asic Physical Design job openings:
What states have the most Asic Physical Design jobs? States with the most job openings for Asic Physical Design jobs include:
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Asic Physical Design jobs near you
Infographic showing various Asic Physical Design job openings in the United States as of July 2026, with employment types broken down into 95% Full Time, 1% Part Time, 2% Contract, and 2% Summer. Highlights an 89% Physical, 6% Hybrid, and 5% Remote job distribution, with an average salary of $139,408 per year, or $67 per hour.
ASIC Digital Physical Design Manager

ASIC Digital Physical Design Manager

Keysight Technologies, Inc.

Colorado Springs, CO • On-site

$134K - $138K/yr

Full-time

Medical, Dental, Vision, Life, Retirement, PTO

Posted 12 days ago

Keysight Technologies rating

8.1

Company rating: 8.1 out of 10

Based on 20 frontline employees who took The Breakroom Quiz

41st of 142 rated electronics manufacturers

Job description

Overview
Keysight is at the forefront of technology innovation, delivering breakthroughs and trusted insights in electronic design, simulation, prototyping, test, manufacturing, and optimization. Our ~15,000 employees create world-class solutions in communications, 5G, automotive, energy, quantum, aerospace, defense, and semiconductor markets for customers in over 100 countries. Learn more about what we do.
Our award-winning culture embraces a bold vision of where technology can take us and a passion for tackling challenging problems with industry-first solutions. We believe that when people feel a sense of belonging, they can be more creative, innovative, and thrive at all points in their careers.
This role sits within Keysight Laboratories-a globally recognized technology organization that enables Keysight to be first to market with breakthrough, highly differentiated solutions. Our team of senior engineers has delivered generations of innovation across ASIC and product development, spanning the breadth of the technology landscape. You'll join a high-performance, globally connected engineering organization designing and delivering next-generation Digital and Mixed signal ASICs.
A sustained driver of Keysight's success is the creation and deployment of breakthrough digital and mixed-signal ASICs that unlock step-function performance and customer value in new products. We are seeking an ASIC Physical Design R&D Manager to lead our ASIC Physical Design team-overseeing end-to-end physical implementation and ensuring designs meet aggressive performance, power, and area targets through tapeout and into product development.
The position is based in Colorado Springs at the foot of Pikes Peak, with a purpose-built development campus that brings engineering, advanced technology development, assembly, and machining together in one location. Outside the lab, the campus supports an active lifestyle with on-site fitness and recreation, and Colorado Springs offers exceptional quality of life-immediate access to world-class outdoor activities, year-round recreation, and more than 300 days of sunshine each year.
Responsibilities
  • Drive the physical design technical strategy across programs, including floorplanning, power architecture, and implementation trade-offs to meet PPA (performance, power, area) targets.
  • Lead, mentor, and grow a high-performing Physical Design team; set clear expectations for technical rigor, execution, and delivery.
  • Oversee physical implementation for digital, mixed-signal, and third-party IP-from block to subsystem to top-level integration-including place and route, timing closure, and power closure.
  • Coordinate closely with RTL/design, DFT/test, packaging, and systems teams to ensure clean handoffs, rapid issue resolution, and aligned delivery through tapeout.
  • Own and continuously improve the Physical Design flow, including methodology, automation, CI/regression infrastructure, and best-practice enablement for predictability and quality.
  • Lead physical verification and signoff (DRC/LVS, STA, power/IR/EM, reliability as applicable) and drive tape release readiness with clear signoff criteria.
  • Serve as the primary physical design interface to external CMOS/BiCMOS foundries and partners, ensuring alignment on PDKs, signoff requirements, and tapeout execution.
  • Own project execution across the physical design lifecycle-planning, resourcing, schedules, milestones, and risk mitigation-to deliver predictable tapeouts and product readiness.

Qualifications
Must-have Qualifications
  • B.S. or M.S. in Electrical Engineering or Computer Engineering (or equivalent experience).
  • 7+ years of relevant experience in digital ASIC physical design, including successful tape releases.
  • 5+ years of project/program management experience, including planning, dependency management, risk tracking, and cross-team execution to tapeout.

Preferred Qualifications
  • Demonstrated people leadership, including mentoring and coaching engineers, developing future technical leaders, and building an inclusive, high-accountability culture.
  • Expertise in physical implementation and layout methodology, including timing closure, signoff, and power/performance/area optimization.
  • Working knowledge of DFT methodologies (e.g., scan insertion/test considerations) and how they impact physical design, closure, and tape release.
  • Strong EE fundamentals with experience spanning ASIC design concepts, IP integration, and CMOS/BiCMOS processes.
  • Strong teamwork and problem-solving skills, with clear written and verbal communication across engineering and program stakeholders.
  • Leadership skills to drive change and influence cross-functional teams toward execution goals, quality, and predictable delivery.
  • Sound technical judgment under schedule pressure, with a track record of making effective PPA trade-offs while maintaining signoff quality.

ITAR statement: This position requires access to certain goods, software, technology, or technical data subject to U.S. export control laws and regulations. Under these laws and regulations, U.S. persons (which includes U.S. citizens, U.S. nationals, lawful permanent residents, refugees, and asylees) working for Keysight can access export-controlled items without authorization from the U.S. government. For any individual who is not a U.S. person, Keysight may need authorization from the U.S. Department of State, U.S. Department of Commerce, or other appropriate federal agency before the individual can access export-controlled items. Employment in this position for non-U.S. persons is contingent on Keysight's ability to obtain any required government authorizations.
We are unable to support visa sponsorship for this position.
MIN $151,000.00 - MAX $253,000.00
Most offers will be between the minimum and the midpoint of the Salary Range listed above.
#LI-MO1
Note: For other locations, pay ranges will vary by region
US Employees may be eligible for the following benefits:
  • Medical, dental and vision
  • Health Savings Account
  • Health Care and Dependent Care Flexible Spending Accounts
  • Life, Accident, Disability insurance
  • Business Travel Accident and Business Travel Health
  • 401(k) Plan
  • Flexible Time Off, Paid Holidays
  • Paid Family Leave
  • Discounts, Perks
  • Tuition Reimbursement
  • Adoption Assistance
  • ESPP (Employee Stock Purchase Plan)

Careers Privacy Statement***Keysight is an Equal Opportunity Employer.***

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