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Asic Physical Design Jobs in Texas (NOW HIRING)

Cisco

ASIC Physical Design Engineer

Austin, TX

$128K - $184K/yr

Your Impact As a Physical Design Engineer with Acacia, you will focus on the technical execution of high-performance ASIC designs. Working as an individual contributor, you will lead the RTL-to-GDSII ...

Meta

ASIC Engineer, Physical Design

Austin, TX

$178K/yr

ASIC Engineer, Physical Design Responsibilities: * Lead physical implementation of complex ASIC blocks or full chips, including floorplanning, placement, clock tree synthesis, routing, and signoff ...

Cisco

ASIC Physical Design Technical Lead

Austin, TX · On-site

$186K - $267K/yr

Experience with hierarchical design, timing closure, physical design convergence, and power integrity analysis. * Experience with static timing analysis and concepts, defining timing constraints and ...

Qualcomm

Physical Design Engineer - DSP Team

Austin, TX · On-site

$164 - $246/hr

Bachelor's degree in Science, Engineering, or related field * 12+ years ASIC Physical design, Synthesis or related work experience * Strong proficiency in P&R, timing analysis, CAD tools (e.g ...

Apple

SoC Physical Design Verification Engineer

Austin, TX · On-site

$134K - $138K/yr

... ASIC physical design and physical verification checks Scripting skills perl/python/tcl to debug flow related issues and automate checks Experienced in industry standard tools used for physical ...

Apple

SoC Physical Design Verification Engineer

Austin, TX · On-site

$134K - $138K/yr

... of ASIC physical design and physical verification checks for hierarchical designs including full-chip flows Scripting skills perl/python/tcl to debug flow related issues and automate checks ...

Cisco

ASIC Physical Design Technical Lead

Austin, TX · On-site

$183K - $263K/yr

Bachelor's Degree in Electrical Engineering with 8+ years of Physical Design experience or Master's Degree in Electrical Engineering with 6+ years of Physical Design experience, or PhD in Electrical ...

Qualcomm

Physical Design Engineer - DSP Team

Austin, TX · On-site

$134K - $138K/yr

Bachelor's degree in Science, Engineering, or related field. * 12+ years ASIC Physical design, Synthesis or related work experience * Strong proficiency in P&R, timing analysis, CAD tools (e.g ...

Nvidia

CPU Design Methodology Engineer

Austin, TX

In this position, you will get the chance to build complex chips and interact directly with unit-level ASIC, Physical Design, CAD, Package Design, Software, DFT and other teams. What you'll be doing:

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Asic Physical Design information

See Texas salary details

$88.5K

$131.8K

How much do asic physical design jobs pay per year?

As of Aug 19, 2026, the average yearly pay for asic physical design in Texas is $129,881.00, according to ZipRecruiter salary data. Most workers in this role earn between $126,700.00 and $130,400.00 per year, depending on experience, location, and employer.

What is an ASIC Physical Design engineer?

ASIC Physical Design engineers are professionals who take a digital circuit design and transform it into a physical layout that can be manufactured as an integrated circuit (IC) chip. They are responsible for tasks like floorplanning, placement, clock tree synthesis, routing, and ensuring the chip meets timing, power, and area requirements. Their work is critical in bridging the gap between a chip's logical design and its actual fabrication in silicon. ASIC Physical Design engineers use Electronic Design Automation (EDA) tools to optimize and verify the chip design before manufacturing. They play a key role in delivering high-performance, reliable, and cost-effective semiconductors.

What are the key skills and qualifications needed to thrive as an ASIC Physical Design engineer?

To thrive as an ASIC Physical Design Engineer, you need a solid background in electrical engineering, digital logic design, and experience with the ASIC design flow, often supported by a relevant degree. Proficiency with EDA tools such as Cadence, Synopsys, or Mentor Graphics, and familiarity with scripting languages like TCL or Perl, are typically required. Strong problem-solving skills, attention to detail, and effective communication enhance collaboration within cross-functional teams. These capabilities ensure the efficient design, optimization, and delivery of high-performance, manufacturable integrated circuits.

What are some common challenges faced by ASIC Physical Design engineers during the tape-out phase, and how can they be addressed?

ASIC Physical Design engineers often encounter challenges such as meeting tight timing closure requirements, resolving signal integrity issues, and managing power consumption during the tape-out phase. These challenges require close collaboration with verification, synthesis, and DFT teams, as well as the use of industry-standard EDA tools for thorough analysis and optimization. Proactive communication, rigorous design reviews, and adopting a structured sign-off checklist can help address potential bottlenecks and ensure a successful tape-out.

What is the difference between Asic Physical Design vs Asic Verification Engineer?

AspectAsic Physical DesignAsic Verification Engineer
Primary FocusImplementing physical layout, placement, routing of ASICsVerifying functionality and performance of ASIC designs
Skills & CertificationsVLSI design, EDA tools, CMOS fabrication knowledgeHardware description languages, simulation tools, testbench development
Work EnvironmentDesign teams, CAD tools, EDA softwareSimulation labs, testing environments, design verification teams
Industry UsageFoundries, semiconductor companies, chip design firmsASIC design companies, semiconductor firms, EDA tool providers

While both roles are integral to ASIC development, Asic Physical Design focuses on the physical implementation of chip layouts, whereas Asic Verification Engineer concentrates on testing and validating the design to ensure it meets specifications.

What are popular job titles related to Asic Physical Design jobs in Texas?

For Asic Physical Design jobs in Texas, the most frequently searched job titles are:

What job categories do people searching Asic Physical Design jobs in Texas look for?

The top searched job categories for Asic Physical Design jobs in Texas are:

What cities in Texas are hiring for Asic Physical Design jobs?

Cities in Texas with the most Asic Physical Design job openings:

Asic Physical Design jobs near you
Infographic showing various Asic Physical Design job openings in Texas as of August 2026, with employment types broken down into 1% As Needed, 79% Full Time, 16% Part Time, 1% Temporary, 2% Contract, and 1% Nights. Highlights an 97% Physical, 1% Hybrid, and 2% Remote job distribution, with an average salary of $129,881 per year, or $62.4 per hour.

Sr. SOC/ASIC Physical Design Engineer (Silicon Engineering)

SpaceX

Austin, TX • On-site

Full-time

Re-posted 24 days ago

SpaceX rating

8.7

Company rating: 8.7 out of 10

Based on 148 frontline employees who took The Breakroom Quiz

17th of 72 rated aerospace companies

Job description

SR. SOC/ASIC PHYSICAL DESIGN ENGINEER (SILICON ENGINEERING)

At SpaceX we're leveraging our experience in building rockets and spacecraft to deploy Starlink, the world's most advanced broadband internet system. Starlink is the world's largest satellite constellation and is providing fast, reliable internet to millions of users worldwide. We design, build, test, and operate all parts of the system - thousands of satellites, consumer receivers that allow users to connect within minutes of unboxing, and the software that brings it all together. We've only begun to scratch the surface of Starlink's potential global impact and are looking for best-in-class engineers to help maximize Starlink's utility for communities and businesses around the globe. 

We are seeking a motivated, proactive, and intellectually curious engineer who will work alongside world-class cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation). In this role, you will be developing cutting-edge next-generation silicon for deployment in space and ground infrastructures around the globe. These chips are enabling connectivity in places it has previously not been available, affordable or reliable. Your efforts will help deliver cutting-edge solutions that will expand the performance and capabilities of the Starlink network.   

RESPONSIBILITIES:

  • Perform partition synthesis and physical implementation steps (e.g. synthesis, floorplanning, power/ground grid generation, place and route, timing, noise, physical verification, electromigration, voltage drop, logic equivalency and other signoff checks)
  • Develop/improve physical design methodologies and automation scripts for various implementation steps
  • Closely collaborate with the ASIC design team to drive architectural feasibility studies, develop timing, power and area design targets, and explore RTL/design tradeoffs
  • Resolve design/timing/congestion and flow issues, identify potential solutions and drive execution
  • Run, debug, and fix signoff closure issues in static timing analysis (STA), noise, logic equivalency, physical verification, electromigration and voltage drop

BASIC QUALIFICATIONS:

  • Bachelor's degree in electrical engineering, computer engineering or computer science
  • 5+ years of ASIC and/or physical design flow development experience in industry

PREFERRED SKILLS AND EXPERIENCE:

  • Strong experience in ASIC/SOC RTL2GDSII physical design and signoff flows
  • Strong experience with industry standard EDA tools including understanding of their capabilities and underlying algorithms
  • Knowledge of deep sub-micron FinFET and CMOS solid state physics
  • Knowledge of CMOS digital design principles, basic standard cells their functionality, standard cell libraries
  • Understanding of CMOS power dissipation in deep submicron processes leakage/dynamic
  • Familiar with CMOS analog circuit and physical design
  • Knowledge of DFT/Scan/MBIST/LBIST and understanding of their impact on physical design flows
  • Good scripting skills (csh/bash, Perl, Python, TCL, Makefile etc.)
  • Self-driven individual with a can-do attitude, willing to learn, and an ability to work in a dynamic group environment

ADDITIONAL REQUIREMENTS:    

  • Ability to work extended hours and weekends as needed to meet critical project milestones   

What SpaceX employees say

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Hours and flexibility

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About SpaceX

Sourced by ZipRecruiter

Industry

Aerospace product and parts manufacturing, data services, guided missile and space vehicle manufacturing and satellite telecommunications

Company size

1,001 - 5,000 Employees

Headquarters location

Hawthorne, CA, US

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