ZipRecruiter

Log In

1

Asic Physical Design Jobs in Seattle, WA (NOW HIRING)

K2 Space

Senior ASIC Physical Design Engineer

Seattle, WA · On-site

$170K - $250K/yr

The Role We are seeking a Senior ASIC Physical Design Engineer to help implement advanced SoCs that power next-generation satellite and space systems. In this role, you will contribute to the full ...

Mundi

Principal ASIC Physical Design Engineer

Seattle, WA · On-site

$190 - $280/hr

The Role We are looking for a Principal ASIC Physical Design Engineer to lead the implementation of complex SoCs for next‑generation satellite and space systems. You will own the full physical ...

K2 Space

Senior ASIC Physical Design Engineer

Seattle, WA · On-site

$170K - $250K/yr

The Role We are seeking a Senior ASIC Physical Design Engineer to help implement advanced SoCs that power next-generation satellite and space systems. In this role, you will contribute to the full ...

K2 Space

Principal ASIC Physical Design Engineer

Seattle, WA · On-site

$190K - $280K/yr

The Role We are looking for a Principal ASIC Physical Design Engineer to lead the implementation of complex SoCs for next-generation satellite and space systems. You will own the full physical design ...

K2 Space

Principal ASIC Physical Design Engineer

Seattle, WA · On-site

$190K - $280K/yr

The Role We are looking for a Principal ASIC Physical Design Engineer to lead the implementation of complex SoCs for next-generation satellite and space systems. You will own the full physical design ...

K2 Space

Senior ASIC Emulation Engineer

Seattle, WA

$170K - $250K/yr

The Role We are seeking a Senior ASIC Emulation Engineer who will lead the bring-up, deployment ... You will work closely with architecture, RTL design, DFT, DV, firmware, physical design, and ...

K2 Space

Senior ASIC Emulation Engineer

Seattle, WA · On-site

$170K - $250K/yr

The Role We are seeking a Senior ASIC Emulation Engineer who will lead the bring-up, deployment ... You will work closely with architecture, RTL design, DFT, DV, firmware, physical design, and ...

K2 Space

Senior ASIC Emulation Engineer

Seattle, WA

$170K - $250K/yr

The Role We are seeking a Senior ASIC Emulation Engineer who will lead the bring-up, deployment ... You will work closely with architecture, RTL design, DFT, DV, firmware, physical design, and ...

next page

Showing results 1-20

All JobsAsic Physical Design JobsAsic Physical Design Jobs in Seattle, WA

Asic Physical Design information

See Seattle, WA salary details

$108.1K

$161K

How much do asic physical design jobs pay per year?

As of Sep 3, 2026, the average yearly pay for asic physical design in Seattle, WA is $158,651.00, according to ZipRecruiter salary data. Most workers in this role earn between $154,800.00 and $159,300.00 per year, depending on experience, location, and employer.

What is an ASIC Physical Design engineer?

ASIC Physical Design engineers are professionals who take a digital circuit design and transform it into a physical layout that can be manufactured as an integrated circuit (IC) chip. They are responsible for tasks like floorplanning, placement, clock tree synthesis, routing, and ensuring the chip meets timing, power, and area requirements. Their work is critical in bridging the gap between a chip's logical design and its actual fabrication in silicon. ASIC Physical Design engineers use Electronic Design Automation (EDA) tools to optimize and verify the chip design before manufacturing. They play a key role in delivering high-performance, reliable, and cost-effective semiconductors.

What are the key skills and qualifications needed to thrive as an ASIC Physical Design engineer?

To thrive as an ASIC Physical Design Engineer, you need a solid background in electrical engineering, digital logic design, and experience with the ASIC design flow, often supported by a relevant degree. Proficiency with EDA tools such as Cadence, Synopsys, or Mentor Graphics, and familiarity with scripting languages like TCL or Perl, are typically required. Strong problem-solving skills, attention to detail, and effective communication enhance collaboration within cross-functional teams. These capabilities ensure the efficient design, optimization, and delivery of high-performance, manufacturable integrated circuits.

What are some common challenges faced by ASIC Physical Design engineers during the tape-out phase, and how can they be addressed?

ASIC Physical Design engineers often encounter challenges such as meeting tight timing closure requirements, resolving signal integrity issues, and managing power consumption during the tape-out phase. These challenges require close collaboration with verification, synthesis, and DFT teams, as well as the use of industry-standard EDA tools for thorough analysis and optimization. Proactive communication, rigorous design reviews, and adopting a structured sign-off checklist can help address potential bottlenecks and ensure a successful tape-out.

What is the difference between Asic Physical Design vs Asic Verification Engineer?

AspectAsic Physical DesignAsic Verification Engineer
Primary FocusImplementing physical layout, placement, routing of ASICsVerifying functionality and performance of ASIC designs
Skills & CertificationsVLSI design, EDA tools, CMOS fabrication knowledgeHardware description languages, simulation tools, testbench development
Work EnvironmentDesign teams, CAD tools, EDA softwareSimulation labs, testing environments, design verification teams
Industry UsageFoundries, semiconductor companies, chip design firmsASIC design companies, semiconductor firms, EDA tool providers

While both roles are integral to ASIC development, Asic Physical Design focuses on the physical implementation of chip layouts, whereas Asic Verification Engineer concentrates on testing and validating the design to ensure it meets specifications.

What are popular job titles related to Asic Physical Design jobs in Seattle, WA?

For Asic Physical Design jobs in Seattle, WA, the most frequently searched job titles are:

What job categories do people searching Asic Physical Design jobs in Seattle, WA look for?

The top searched job categories for Asic Physical Design jobs in Seattle, WA are:

Asic Physical Design jobs near you
Infographic showing various Asic Physical Design job openings in Seattle, WA as of August 2026, with employment types broken down into 1% As Needed, 74% Full Time, 19% Part Time, 1% Temporary, 4% Contract, and 1% Nights. Highlights an 97% Physical, 1% Hybrid, and 2% Remote job distribution, with an average salary of $158,651 per year, or $76.3 per hour.

Senior ASIC Physical Design Engineer

K2 Space

Seattle, WA

$170K - $250K/yr

Full-time

Medical, Dental, Vision, Life, PTO

Re-posted 3 days ago

Job description

The Role 

We are seeking a Senior ASIC Physical Design Engineer to help implement advanced SoCs that power next-generation satellite and space systems. In this role, you will contribute to the full physical design flow-from synthesis to GDSII-working closely with architecture, RTL, verification, and packaging teams. You'll be a key contributor in achieving timing closure, optimizing PPA, and supporting design integration with external partners. You will be part of a collaborative design team developing state-of-the-art mixed-signal SoCs to be hosted on some of the largest, most powerful, rapidly designed and rapidly manufactured satellites ever deployed in space. In your first 6 months, you will develop and implement new SoC sub-systems for satellite communications and beyond. In your first two years, you will have contributed to developing cutting-edge SoCs that will fly in space. 

Responsibilities 

  • Execute the complete physical design flow for complex SoC blocks and top-level integration, including synthesis, floorplanning, place & route, CTS, STA, and physical verification. 
  • Perform timing closure and optimization across multiple corners and modes using industry-standard tools. 
  • Collaborate with front-end, verification, and DFT teams to ensure clean handoff and predictable convergence. 
  • Work with external physical design service providers and internal leads to review deliverables, resolve issues, and ensure schedule alignment. 
  • Develop and maintain scripts and automation to improve flow efficiency and consistency. 
  • Support physical sign-off activities including DRC/LVS, IR drop, EM, and power analysis. 
  • Assist in chip-level integration, ECOs, and tapeout preparation. 
  • Contribute to methodology development, tool evaluation, and flow documentation. 
  • Support your product through production and spaceflight.  

Required Qualifications 

  • Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field. 
  • 5-10 years of experience in ASIC physical design for complex SoCs. 
  • Hands-on experience with industry-standard tools (Synopsys ICC2/Fusion Compiler, Cadence Innovus, or equivalent). 
  • Strong understanding of timing analysis, power optimization, and physical verification flows. 
  • Experience with hierarchical or flat SoC design methodologies. 
  • Familiarity with FinFET technologies. 
  • Working knowledge of DFT, UPF/CPF power intent, and ECO implementation. 
  • Strong problem-solving skills and ability to work cross-functionally in fast-paced environments. 

Preferred Qualifications 

  • Exposure to radiation-hardened or space-qualified ASICs. 
  • Experience with chip-package co-design or advanced packaging (2.5D/3D). 
  • Familiarity with physical design service vendor management or offshore collaboration. 
  • Experience with sign-off through TSMC. 
  • Experience with Gate-All-Around technologies.  
  • Experience working in cross-functional, geographically distributed teams. 

Compensation and Benefits:

  • Base salary range for this role is $170,000 - $250,000 + equity in the company
  • Salary will be based on several factors including, but not limited to: knowledge and skills, education, and experience level
  • Comprehensive benefits package including paid time off, medical/dental/vision/ coverage, life insurance, paid parental leave, and many other perks
K2 Space logo

About K2 Space

Sourced by ZipRecruiter

Industry

Guided missile and space vehicle manufacturing

Company size

11 - 50 Employees

Headquarters location

Los Angeles, CA, US

Year founded

2022

View All K2 Space Jobs

Apply