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Physical Design Engineer Jobs in Seattle, WA (NOW HIRING)

K2 Space

Senior ASIC Physical Design Engineer

Seattle, WA · On-site

$170K - $250K/yr

The Role We are seeking a Senior ASIC Physical Design Engineer to help implement advanced SoCs that power next-generation satellite and space systems. In this role, you will contribute to the full ...

K2 Space

Senior ASIC Physical Design Engineer

Seattle, WA · On-site

$170K - $250K/yr

The Role We are seeking a Senior ASIC Physical Design Engineer to help implement advanced SoCs that power next-generation satellite and space systems. In this role, you will contribute to the full ...

Amazon

Sr. Mechanical Design Engineer

Redmond, WA · On-site

$100K - $138K/yr

The Sr. Mechanical Design Engineer will be a member of the Amazon Leo Inter-Satellite Link team ... physical design, while optimizing to support high volume production and meeting cross discipline ...

Amazon

Sr. Mechanical Design Engineer

Redmond, WA

$100K - $138K/yr

The Sr. Mechanical Design Engineer will be a member of the Amazon Leo Inter-Satellite Link team ... physical design, while optimizing to support high volume production and meeting cross discipline ...

Amazon

Sr. Mechanical Design Engineer

Redmond, WA · On-site

$100K - $138K/yr

The Sr. Mechanical Design Engineer will be a member of the Amazon Leo Inter-Satellite Link team ... physical design, while optimizing to support high volume production and meeting cross discipline ...

ATS Automation

Design Engineer

Renton, WA · On-site

$68K - $124K/yr

The Design Engineer is a key member of the Engineering Services Group, a centralized team focused ... Strong troubleshooting and problem-solving abilities WORK ENVIRONMENT AND PHYSICAL DEMANDS: This ...

ATS Companies

Design Engineer

Renton, WA · On-site

$68K - $124K/yr

The Design Engineer is a key member of the Engineering Services Group, a centralized team focused ... Strong troubleshooting and problem-solving abilities WORK ENVIRONMENT AND PHYSICAL DEMANDS: This ...

ATS Companies

Design Engineer

Renton, WA

$68K - $124K/yr

The Design Engineer is a key member of the Engineering Services Group, a centralized team focused ... Strong troubleshooting and problem-solving abilities WORK ENVIRONMENT AND PHYSICAL DEMANDS: This ...

amphenol

Design Engineer

Seattle, WA · Hybrid

SUMMARY We are seeking an experienced engineer to join our team and contribute to the design and ... Work is performed in a normal office environment with minimal physical risks involved. The noise ...

Amphenol

Design Engineer

Seattle, WA · On-site

SUMMARY We are seeking an experienced engineer to join our team and contribute to the design and ... Work is performed in a normal office environment with minimal physical risks involved. The noise ...

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Physical Design Engineer information

See Seattle, WA salary details

$108.1K

$161K

How much do physical design engineer jobs pay per year?

As of Aug 3, 2026, the average yearly pay for physical design engineer in Seattle, WA is $158,648.00, according to ZipRecruiter salary data. Most workers in this role earn between $154,800.00 and $159,300.00 per year, depending on experience, location, and employer.

What is a physical design engineer?

A Physical Design Engineer is responsible for transforming logical circuit designs into a physical layout that can be manufactured as an integrated circuit (IC). They focus on key aspects like floor planning, placement, clock tree synthesis (CTS), routing, and timing closure while ensuring power and performance optimization. They work with Electronic Design Automation (EDA) tools and collaborate with front-end designers to meet design specifications. The role requires proficiency in tools such as Cadence, Synopsys, or Mentor Graphics and knowledge of processes like ASIC or SoC design.

What are the key skills and qualifications needed to thrive as a physical design engineer?

To thrive as a Physical Design Engineer, you need a solid background in electrical engineering, experience with ASIC or SoC design methodologies, and a deep understanding of digital circuit fundamentals. Proficiency with EDA tools like Synopsys, Cadence, or Mentor Graphics, as well as familiarity with scripting languages and industry certifications, is highly valued. Attention to detail, effective teamwork, and strong problem-solving skills are essential soft skills for this role. These qualifications are crucial as they enable efficient chip design, ensure successful project delivery, and foster productive collaboration in complex engineering environments.

What are the typical daily responsibilities of a physical design engineer?

As a Physical Design Engineer, your daily responsibilities typically include taking logical circuit designs and translating them into physical layouts, performing floorplanning, placement, and routing of blocks, and conducting timing closure and verification. You will use specialized EDA tools to ensure that designs meet performance, power, and area requirements, collaborating closely with design, verification, and manufacturing teams. The role also involves resolving design issues, optimizing chip layouts, and preparing design data for fabrication. Working in this position provides exposure to advanced technology nodes and the opportunity to contribute directly to the development of cutting-edge semiconductor products.

What are the most commonly searched types of Physical Design Engineer jobs in Seattle, WA? The most popular types of Physical Design Engineer jobs in Seattle, WA are:
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Physical Design Engineer jobs near you
Infographic showing various Physical Design Engineer job openings in Seattle, WA as of July 2026, with employment types broken down into 83% Full Time, and 17% Part Time. Highlights an 100% In-person job distribution, with an average salary of $158,648 per year, or $76.3 per hour.

Principal ASIC Physical Design Engineer

K2 Space

Seattle, WA • On-site

$190K - $280K/yr

Other

Medical, Dental, Vision, Life, PTO

Re-posted 4 days ago

Job description

The Role

We are looking for a Principal ASIC Physical Design Engineer to lead the implementation of complex SoCs for next-generation satellite and space systems. You will own the full physical design flow-from RTL handoff to GDSII-and collaborate closely with architecture, RTL design, DFT, and packaging teams. This role also involves managing external physical design partners, driving tool and flow decisions, and ensuring first-pass silicon success in advanced FinFET technologies. You'll be a key contributor in achieving timing closure, optimizing PPA, and supporting design integration with external partners. You will be part of a collaborative design team developing state-of-the-art mixed-signal SoCs to be hosted on some of the largest, most powerful, rapidly designed and rapidly manufactured satellites ever deployed in space. In your first 6 months, you will develop and implement new SoC sub-systems for satellite communications and beyond. In your first two years, you will have contributed to developing cutting-edge SoCs that will fly in space. 

Responsibilities

  • Own the complete RTL-to-GDSII flow: synthesis, floorplanning, place & route, clock tree synthesis (CTS), static timing analysis (STA), physical verification (DRC/LVS), and sign-off.
  • Develop and maintain physical design methodologies, scripts, and automation to optimize performance, power, and area (PPA).
  • Collaborate with front-end and verification teams to ensure clean handoffs, timing closure, and efficient design iteration.
  • Drive timing closure across multiple voltage and process corners, including sign-off with foundry-qualified tools.
  • Partner with package, SI/PI, and test teams for package-aware floorplanning and chip-to-board integration.
  • Manage and technically guide external physical design partners and service vendors, ensuring alignment on milestones, deliverables, and quality standards.
  • Work with EDA vendors to debug and optimize tool flows, and evaluate new methodologies.
  • Support chip bring-up and debug through close collaboration with post-silicon and test teams.
  • Support your product through production and spaceflight.

Required Qualifications 

  • Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field.
  • 10+ years of experience in ASIC physical design for high-performance SoCs.
  • Proven end-to-end expertise in RTL-to-GDSII flows using industry tools (Synopsys, Cadence, or Siemens).
  • Strong hands-on experience with timing closure, IR drop analysis, and ECO implementation.
  • Deep understanding of physical design constraints for multi-clock, multi-voltage, and hierarchical SoCs.
  • Experience with advanced FinFET process nodes.
  • Prior experience managing or coordinating offshore/outsourced PD teams or vendors.
  • Familiarity with DFT integration, STA sign-off, and power domain implementation (UPF/CPF).
  • Excellent communication, leadership, and cross-functional collaboration skills.
  • Act as technical leader and subject-matter expert helping to teach, grow, and mentor others in the team.

Preferred Qualifications 

  • Exposure to radiation-hardened or space-qualified ASICs.
  • Experience with chip-package co-design or advanced packaging (2.5D/3D).
  • Familiarity with physical design service vendor management or offshore collaboration.
  • Experience driving tapeouts through TSMC.
  • Experience with Gate-All-Around technologies.
  • Experience working in cross-functional, geographically distributed teams.

Compensation and Benefits:

  • Base salary range for this role is $190,000 - $280,000 + equity in the company
  • Salary will be based on several factors including, but not limited to: knowledge and skills, education, and experience level
  • Comprehensive benefits package including paid time off, medical/dental/vision/ coverage, life insurance, paid parental leave, and many other perks
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About K2 Space

Sourced by ZipRecruiter

Industry

Guided missile and space vehicle manufacturing

Company size

11 - 50 Employees

Headquarters location

Los Angeles, CA, US

Year founded

2022

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