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Rtl Design Jobs in Seattle, WA (NOW HIRING)

Digital RTL Engineer

Seattle, WA ยท On-site

$120 - $180/hr

The Role We're looking for a Digital RTL Engineer to design the digital control, beamforming, and interface logic at the heart of our phased array solutions. As one of our early digital hires, you ...

New

Sr DSP / RTL Engineer

Seattle, WA ยท On-site

$140 - $190/hr

You'll work end-to-end: algorithm design and modeling, fixed-point conversion, RTL coding and synthesis, timing closure, and lab validation. The decisions you make will directly shape system ...

New

Senior FPGA Engineer

Redmond, WA ยท On-site

$215K - $250K/yr

Kapta Space is seeking a Senior FPGA Engineer to lead RTL design and FPGA development for radar operation and algorithm implementation. Kapta Space is seeking FPGA Engineers with experience in ...

Senior FPGA Engineer

Redmond, WA ยท On-site

$215 - $250/hr

Kapta Space is seeking a Senior FPGA Engineer to lead RTL design and FPGA development for radar operation and algorithm implementation. Kapta Space is seeking FPGA Engineers with experience in ...

Senior ASIC Emulation Engineer

Seattle, WA ยท On-site

$170K - $250K/yr

You will work closely with architecture, RTL design, DFT, DV, firmware, physical design, and silicon validation teams to enable highfidelity hardware/software co-development and accelerate ...

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Showing results 1-20

Rtl Design information

See Seattle, WA salary details

$91.6K

$158.6K

$207.7K

How much do rtl design jobs pay per year?

As of Sep 6, 2026, the average yearly pay for rtl design in Seattle, WA is $158,604.00, according to ZipRecruiter salary data. Most workers in this role earn between $154,800.00 and $154,800.00 per year, depending on experience, location, and employer.

What is an RTL design?

An RTL (Register Transfer Level) Design job involves designing and implementing digital circuits using hardware description languages (HDLs) like Verilog or VHDL. RTL engineers translate high-level specifications into synthesizable logic, ensuring functionality, power efficiency, and performance. They collaborate with verification engineers to test and debug designs before fabrication. This role is crucial in developing ASICs, FPGAs, and other digital hardware components.

What does an RTL design engineer do?

A typical day for an RTL Design engineer involves writing and optimizing RTL code, running simulations, debugging designs, and reviewing results from verification teams. Collaboration is key, as you will frequently interact with verification engineers, physical design teams, and architects to ensure the design meets both functional and performance requirements. You may also participate in design reviews, resolve issues found during testing, and work with project managers to meet deadlines. This cross-functional teamwork creates a dynamic environment where communication and problem-solving skills are highly valued, helping ensure the successful delivery of silicon products.

What are the key skills and qualifications needed for RTL design?

To thrive as an RTL Design engineer, you need a solid background in digital logic design, computer architecture, and proficiency in hardware description languages such as Verilog or VHDL, typically supported by a degree in electrical or computer engineering. Familiarity with EDA tools like Synopsys, Cadence, or Mentor Graphics, and experience with FPGA/ASIC flows, are highly valuable, as are relevant industry certifications. Strong problem-solving skills, attention to detail, and effective communication foster successful collaboration with verification and physical design teams. These skills are crucial for delivering robust, efficient hardware solutions in complex chip development projects.

What are the most commonly searched types of Rtl Design jobs in Seattle, WA?

The most popular types of Rtl Design jobs in Seattle, WA are:

Infographic showing various Rtl Design job openings in Seattle, WA as of August 2026, with employment types broken down into 88% Full Time, 8% Part Time, and 4% Contract. Highlights an 86% Physical, 4% Hybrid, and 10% Remote job distribution, with an average salary of $158,604 per year, or $76.3 per hour.

Digital RTL Engineer

Roguebeam

Seattle, WA โ€ข On-site

$120 - $180/hr

Other

Posted 3 days ago

New


Job description

The Role

Weโ€™re looking for a Digital RTL Engineer to design the digital control, beamforming, and interface logic at the heart of our phased array solutions. As one of our early digital hires, you wonโ€™t just execute against a spec handed down to youโ€”youโ€™ll contribute to the architecture and design methodology behind our products and help shape how the team works as it grows.

Youโ€™ll own digital RTL design from architecture through synthesis, timing closure, and silicon/FPGA bring-up, working closely with RFIC, antenna, and DSP teams. The decisions you make will ripple through every product we build.

Responsibilities
  • Design and implement digital RTL (SystemVerilog/Verilog) for beamformer control, phase/amplitude control interfaces, calibration logic, high-speed data paths, and system-level digital blocks

  • Drive designs from specification and architecture definition through RTL coding, synthesis, timing analysis, place-and-route support, and silicon/FPGA validation

  • Perform functional simulation, lint, CDC analysis, and timing closure; collaborate on verification planning and coverage

  • Work with RFIC, antenna, and DSP teams to define digital interfaces, control protocols, and system-level requirements

  • Support lab bring-up, debug, and design iteration of fabricated ASICs or FPGA-based prototypes

  • Contribute to design reviews, documentation, and the technical culture of a growing company

Minimum Qualifications
  • Bachelorโ€™s degree in Electrical Engineering, Computer Engineering, or a related field

  • 3โ€“5 years of relevant experience in digital RTL design for ASICs or FPGAs

  • Strong proficiency in SystemVerilog/Verilog and industry-standard tools (e.g., Cadence/Synopsys synthesis & STA, simulation environments, lint/CDC tools)

  • Solid understanding of digital design fundamentals: synchronous design, timing closure, clock-domain crossing, finite-state machines, and high-speed interfaces

Preferred Qualifications
  • MSc or PhD with a focus on digital design, computer architecture, or VLSI

  • Experience designing digital control logic for RF beamformers, phased arrays, or similar high-performance systems

  • Familiarity with high-speed serial interfaces, AXI/APB buses, and low-power design techniques

  • Experience taking designs through synthesis, timing closure, and post-silicon or FPGA validation

  • Background in communications or radar system requirements

  • Exposure to scripting (Python/Tcl) for design automation and flow development

Why Roguebeam

This is a rare ground-floor opportunity. Joining a startup at this stage means your work has a direct, visible effect on whether the company succeedsโ€”and a corresponding upside as we grow. Because we build the entire system in-house, youโ€™ll see your digital designs integrated into real phased arrays and deployed in working systems, not handed off and forgotten. Youโ€™ll have real ownership and a seat at the table on technical direction.

This position requires access to information controlled under ITAR/EAR; applicants must be U.S. persons as defined in 22 CFR 120.62.

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