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Rtl Design Jobs in Seattle, WA (NOW HIRING)

K2 Space

Senior ASIC Emulation Engineer

Seattle, WA · On-site

$170K - $250K/yr

You will work closely with architecture, RTL design, DFT, DV, firmware, physical design, and silicon validation teams to enable highfidelity hardware/software co-development and accelerate ...

Mundi

Principal ASIC Physical Design Engineer

Seattle, WA · On-site

$190 - $280/hr

You will own the full physical design flow--from RTL handoff to GDSII--and collaborate closely with architecture, RTL design, DFT, and packaging teams. This role also involves managing external ...

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Rtl Design information

See Seattle, WA salary details

$91.6K

$158.6K

$207.7K

How much do rtl design jobs pay per year?

As of Aug 17, 2026, the average yearly pay for rtl design in Seattle, WA is $158,604.00, according to ZipRecruiter salary data. Most workers in this role earn between $154,800.00 and $154,800.00 per year, depending on experience, location, and employer.

What is an RTL design?

An RTL (Register Transfer Level) Design job involves designing and implementing digital circuits using hardware description languages (HDLs) like Verilog or VHDL. RTL engineers translate high-level specifications into synthesizable logic, ensuring functionality, power efficiency, and performance. They collaborate with verification engineers to test and debug designs before fabrication. This role is crucial in developing ASICs, FPGAs, and other digital hardware components.

What does an RTL design engineer do?

A typical day for an RTL Design engineer involves writing and optimizing RTL code, running simulations, debugging designs, and reviewing results from verification teams. Collaboration is key, as you will frequently interact with verification engineers, physical design teams, and architects to ensure the design meets both functional and performance requirements. You may also participate in design reviews, resolve issues found during testing, and work with project managers to meet deadlines. This cross-functional teamwork creates a dynamic environment where communication and problem-solving skills are highly valued, helping ensure the successful delivery of silicon products.

What are the key skills and qualifications needed for RTL design?

To thrive as an RTL Design engineer, you need a solid background in digital logic design, computer architecture, and proficiency in hardware description languages such as Verilog or VHDL, typically supported by a degree in electrical or computer engineering. Familiarity with EDA tools like Synopsys, Cadence, or Mentor Graphics, and experience with FPGA/ASIC flows, are highly valuable, as are relevant industry certifications. Strong problem-solving skills, attention to detail, and effective communication foster successful collaboration with verification and physical design teams. These skills are crucial for delivering robust, efficient hardware solutions in complex chip development projects.

What are popular job titles related to Rtl Design jobs in Seattle, WA?

For Rtl Design jobs in Seattle, WA, the most frequently searched job titles are:

What job categories do people searching Rtl Design jobs in Seattle, WA look for?

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Rtl Design jobs near you
Infographic showing various Rtl Design job openings in Seattle, WA as of August 2026, with employment types broken down into 94% Full Time, and 6% Contract. Highlights an 94% In-person, and 6% Remote job distribution, with an average salary of $158,604 per year, or $76.3 per hour.

Sr. RTL Design Engineer (Silicon Engineering)

SpaceX

Redmond, WA

$165K - $260K/yr

Full-time

Medical, Dental, Vision, Life, Retirement, PTO

Re-posted 28 days ago

SpaceX rating

8.8

Company rating: 8.8 out of 10

Based on 147 frontline employees who took The Breakroom Quiz

14th of 72 rated aerospace companies

Job description

SR. RTL DESIGN ENGINEER (SILICON ENGINEERING) 

At SpaceX we're leveraging our experience in building rockets and spacecraft to deploy Starlink, the world's most advanced broadband internet system. Starlink is the world's largest satellite constellation and is providing fast, reliable internet to millions of users worldwide. We design, build, test, and operate all parts of the system - thousands of satellites, consumer receivers that allow users to connect within minutes of unboxing, and the software that brings it all together. We've only begun to scratch the surface of Starlink's potential global impact and are looking for best-in-class engineers to help maximize Starlink's utility for communities and businesses around the globe. 

We are seeking a motivated, proactive, and intellectually curious engineer who will work alongside world-class cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation). In this role, you will be developing cutting-edge next-generation ASICs for deployment in space and ground infrastructures around the globe. These chips are enabling connectivity in places it has previously not been available, affordable or reliable. Your efforts will help deliver cutting-edge solutions that will expand the performance and capabilities of the Starlink network.   

RESPONSIBILITIES:

  • Evaluate architectural trade-offs based on features, performance requirements and system limitations
  • Define micro-architecture, implement the RTL in Verilog/System Verilog, integrate that in top level and deliver the fully verified, synthesis/timing clean design
  • Work closely with verification team to ensure all aspects of the design are covered and verified
  • Provide timing constraint for those IPs and support the physical implementation team (synthesis, timing closure, formality check)
  • Participate in silicon bring-up and validation

BASIC QUALIFICATIONS:

  • Bachelor's degree in electrical engineering, computer engineering, or computer science
  • 5+ years of experience in RTL implementation

PREFERRED SKILLS AND EXPERIENCE:

  • Ability to solve complex problems including clock domain crossings and power optimization
  • ASIC/SoC system integration experience
  • Experience with embedded CPU subsystems
  • Experience with standard bus protocols (e.g. AXI, AHB, etc.)
  • Experience with high speed and low power design techniques
  • Scripting skills (e.g. Python, etc.)
  • Experience with EDA tools such as HDL simulators and HDL Lint tools
  • Team-player, can-do attitude and ability to work well in a group environment while still contributing on an individual basis
  • Enjoys being challenged and learning new skills

ADDITIONAL REQUIREMENTS:

  • Ability to work extended hours or weekends as needed for mission critical deadlines

COMPENSATION & BENEFITS:    

Pay range:
ASIC Design Engineer/Senior: $165,000.00 - $260,000.00/per year    
Your actual level and base salary will be determined on a case-by-case basis and may vary based on the following considerations: job-related knowledge and skills, education, and experience.

Base salary is just one part of your total rewards package at SpaceX. You may also be eligible for long-term incentives, in the form of company stock, stock options, or long-term cash awards, as well as potential discretionary bonuses and the ability to purchase additional stock at a discount through an Employee Stock Purchase Plan. You will also receive access to comprehensive medical, vision, and dental coverage, access to a 401(k) retirement plan, short & long-term disability insurance, life insurance, paid parental leave, and various other discounts and perks. You may also accrue 3 weeks of paid vacation & will be eligible for 10 or more paid holidays per year. Exempt employees are eligible for 5 days of sick leave per year.

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About SpaceX

Sourced by ZipRecruiter

Industry

Aerospace product and parts manufacturing, data services, guided missile and space vehicle manufacturing and satellite telecommunications

Company size

1,001 - 5,000 Employees

Headquarters location

Hawthorne, CA, US

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