An RTL (Register Transfer Level) Design Engineer is responsible for designing and implementing digital circuits using hardware description languages like VHDL or Verilog. They develop and optimize high-performance, power-efficient designs for ASICs or FPGAs based on system requirements. Their role includes writing RTL code, performing simulations, debugging issues, and collaborating with verification, physical design, and architecture teams. RTL engineers ensure the design meets functional, timing, and power constraints before handing it off for further implementation.