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Soc Design Engineer Jobs in Seattle, WA (NOW HIRING)

K2 Space

Senior ASIC Physical Design Engineer

Seattle, WA · On-site

$170K - $250K/yr

In your first 6 months, you will develop and implement new SoC sub-systems for satellite ... Computer Engineering, or related field. * 5-10 years of experience in ASIC physical design for ...

Actalent

Digital Design Engineer

Kirkland, WA

$60 - $75/hr

Digital Design Engineer This role focuses on the end-to-end design and development of complex, multi-layer digital printed circuit boards (PCBs) for advanced processor, FPGA, and SoC-based systems.

Microsoft

Senior Silicon Design Engineer

Redmond, WA · On-site

$119K - $234K/yr

We are looking for a Senior Design Engineer to work in the dynamic Microsoft Artificial ... SOC) integration on different subsystems. Throughout the program you will be interacting with ...

New

Nvidia

Senior Digital Design Engineer

Redmond, WA

Collaborate with chip architects, verification engineers, formal verification engineers, and SoC ... Deep understanding of ASIC design flows and methodology * Strong analytical and interpersonal ...

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All JobsSoc Design Engineer JobsSoc Design Engineer Jobs in Seattle, WA

Soc Design Engineer information

See Seattle, WA salary details

$46.1K

$100.3K

$180.4K

How much do soc design engineer jobs pay per year?

As of Jul 29, 2026, the average yearly pay for soc design engineer in Seattle, WA is $100,315.00, according to ZipRecruiter salary data. Most workers in this role earn between $77,400.00 and $112,100.00 per year, depending on experience, location, and employer.

What are some typical challenges faced by SoC Design Engineers during the design and verification process?

SoC Design Engineers often encounter challenges such as integrating multiple complex IP blocks, managing power and performance trade-offs, and ensuring design compatibility across different technologies. Verification can be particularly demanding, requiring extensive simulation and debugging to identify subtle hardware bugs or timing issues. Collaboration with software, validation, and layout teams is essential to ensure that the final chip meets all functional and performance specifications.

What is the difference between Soc Design Engineer vs ASIC Design Engineer?

AspectSoc Design EngineerASIC Design Engineer
Required CredentialsBachelor's or Master's in Electrical Engineering, VLSI, or related fields; knowledge of hardware description languagesBachelor's or Master's in Electrical Engineering, VLSI, or related fields; expertise in hardware description languages
Work EnvironmentDesigning integrated systems, collaborating with hardware and software teamsDesigning custom integrated circuits, often in a similar hardware environment
Industry UsageSemiconductor, electronics, embedded systemsSemiconductor, electronics, embedded systems

Soc Design Engineers focus on designing entire system-on-chip solutions, integrating multiple components. ASIC Design Engineers specialize in designing specific custom chips. Both roles require similar credentials and work in comparable environments, often overlapping in industry applications.

What are SoC Design Engineers?

SoC (System on Chip) Design Engineers are professionals who design and develop integrated circuits that combine multiple components such as processors, memory, and peripherals into a single chip. They are responsible for the architecture, verification, and implementation of these complex chips used in devices like smartphones, tablets, and automotive electronics. SoC Design Engineers work with hardware description languages, collaborate with software teams, and ensure the chip meets performance, power, and area requirements. Their role is crucial in the development of efficient, high-performance electronic systems.

What are the key skills and qualifications needed to thrive as a SoC Design Engineer, and why are they important?

To thrive as a SoC Design Engineer, you need a strong background in digital design, computer architecture, and hardware description languages like Verilog or VHDL, typically supported by a degree in electrical or computer engineering. Familiarity with industry-standard EDA tools such as Synopsys, Cadence, and experience with simulation, synthesis, and verification flows is essential. Strong problem-solving skills, attention to detail, and effective communication enable collaboration and innovation in multidisciplinary teams. These skills ensure the development of reliable, high-performance, and cost-effective system-on-chip solutions that meet complex technical requirements.
What are the most commonly searched types of Soc Design Engineer jobs in Seattle, WA? The most popular types of Soc Design Engineer jobs in Seattle, WA are:
What are popular job titles related to Soc Design Engineer jobs in Seattle, WA? For Soc Design Engineer jobs in Seattle, WA, the most frequently searched job titles are:
What job categories do people searching Soc Design Engineer jobs in Seattle, WA look for? The top searched job categories for Soc Design Engineer jobs in Seattle, WA are:
Soc Design Engineer jobs near you
Infographic showing various Soc Design Engineer job openings in Seattle, WA as of July 2026, with employment types broken down into 83% Full Time, 13% Part Time, 1% Temporary, and 3% Contract. Highlights an 84% Physical, 5% Hybrid, and 11% Remote job distribution, with an average salary of $100,373 per year, or $48.3 per hour.

Senior ASIC Physical Design Engineer

K2 Space

Seattle, WA

$170K - $250K/yr

Other

Medical, Dental, Vision, Life, PTO

Posted 28 days ago

Job description

The Role 

We are seeking a Senior ASIC Physical Design Engineer to help implement advanced SoCs that power next-generation satellite and space systems. In this role, you will contribute to the full physical design flow-from synthesis to GDSII-working closely with architecture, RTL, verification, and packaging teams. You'll be a key contributor in achieving timing closure, optimizing PPA, and supporting design integration with external partners. You will be part of a collaborative design team developing state-of-the-art mixed-signal SoCs to be hosted on some of the largest, most powerful, rapidly designed and rapidly manufactured satellites ever deployed in space. In your first 6 months, you will develop and implement new SoC sub-systems for satellite communications and beyond. In your first two years, you will have contributed to developing cutting-edge SoCs that will fly in space. 

Responsibilities 

  • Execute the complete physical design flow for complex SoC blocks and top-level integration, including synthesis, floorplanning, place & route, CTS, STA, and physical verification. 
  • Perform timing closure and optimization across multiple corners and modes using industry-standard tools. 
  • Collaborate with front-end, verification, and DFT teams to ensure clean handoff and predictable convergence. 
  • Work with external physical design service providers and internal leads to review deliverables, resolve issues, and ensure schedule alignment. 
  • Develop and maintain scripts and automation to improve flow efficiency and consistency. 
  • Support physical sign-off activities including DRC/LVS, IR drop, EM, and power analysis. 
  • Assist in chip-level integration, ECOs, and tapeout preparation. 
  • Contribute to methodology development, tool evaluation, and flow documentation. 
  • Support your product through production and spaceflight.  

Required Qualifications 

  • Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field. 
  • 5-10 years of experience in ASIC physical design for complex SoCs. 
  • Hands-on experience with industry-standard tools (Synopsys ICC2/Fusion Compiler, Cadence Innovus, or equivalent). 
  • Strong understanding of timing analysis, power optimization, and physical verification flows. 
  • Experience with hierarchical or flat SoC design methodologies. 
  • Familiarity with FinFET technologies. 
  • Working knowledge of DFT, UPF/CPF power intent, and ECO implementation. 
  • Strong problem-solving skills and ability to work cross-functionally in fast-paced environments. 

Preferred Qualifications 

  • Exposure to radiation-hardened or space-qualified ASICs. 
  • Experience with chip-package co-design or advanced packaging (2.5D/3D). 
  • Familiarity with physical design service vendor management or offshore collaboration. 
  • Experience with sign-off through TSMC. 
  • Experience with Gate-All-Around technologies.  
  • Experience working in cross-functional, geographically distributed teams. 

Compensation and Benefits:

  • Base salary range for this role is $170,000 - $250,000 + equity in the company
  • Salary will be based on several factors including, but not limited to: knowledge and skills, education, and experience level
  • Comprehensive benefits package including paid time off, medical/dental/vision/ coverage, life insurance, paid parental leave, and many other perks
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About K2 Space

Sourced by ZipRecruiter

Industry

Guided missile and space vehicle manufacturing

Company size

11 - 50 Employees

Headquarters location

Los Angeles, CA, US

Year founded

2022

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